Slew rate speed-up circuit

A circuit for improving a response speed of an output signal with respect to an input signal of an operating amplifier having a differential amplifier, said circuit comprising:

• a first output terminal;
• a second output terminal;
• a first pull-up transistor having a gate coupled to an output terminal of said differential amplifier and a channel connected between a power supply voltage terminal and said first output terminal;
• a second pull-up transistors having a gate coupled to said output terminal of said differential amplifier and a channel connected between said power supply voltage terminal and said second output terminal;
• a first pull-down transistor having a channel connected between said first output terminal and a ground voltage terminal;
• a second pull-down transistor having a channel connected between said second output terminal and said ground voltage terminal;
• a third pull-up transistor having a gate coupled to said first output terminal and having a channel connected between said power supply voltage terminal and said second output terminal;
• a third pull-up transistor having a gate coupled to said first output terminal and having a channel connected between said ground voltage terminal and said second output terminal;
• and
• resistive means connected between said first output terminal and said second output terminal.

An amplifier circuit for a semiconductor memory device, comprising:

• differential amplifier means for generating difference signals being a function of differences between first input signals and second input signals received at a first input port and a second input port, respectively;
• a first pull-up transistor having a gate coupled to receive said difference signals and a channel connected between a power voltage node and a first output node;
• a first pull-down transistor having a channel connected between said first output node and a ground voltage node;
• a second pull-up transistor having a gate coupled to receive said difference signals and a channel connected between said power voltage node and a second output node;
• a second pull-down transistor having a channel connected between said ground voltage node and said second output node;
• and
• slew rate means, connected between said first output node and said second output node, for increasing a slew rate of said amplifier circuit.

In an operational amplifier having a differential amplifier coupled to respectively receive first and second input signals, a first pull-up transistor with a gate coupled to receive an output of said differential amplifier and a channel interposed between a power voltage and a first output terminal, a second pull-up transistor with a gate coupled to receive the output of said differential amplifier and a channel interposed between the power voltage and a second output terminal, and a first pull-down transistor with a channel interposed between the first output terminal and ground, and a second pull-down transistor with a channel interposed between the second output terminal and ground, a process for improving a slew rate indicative of a response speed of an output signal from the first output terminal via the second output terminal as a function of said first and second input signals received by said differential amplifier by the steps of:

• providing the output signal from said first output terminal to a gate of a N-MOS transistor having a channel interposed between said power voltage and said second output terminal to enable generation of a current flowing across the first and second output terminals for equalizing the potential between the first and second output terminals in dependence upon a determination of whether the potential of said first output terminal is greater than the potential of said second output terminal to shorten a charging time of said operational amplifier;
• and
• providing the output signal from said first output terminal to a gate of a P-MOS transistor having a channel interposed between said second output terminal and ground to enable said operational amplifier to ground the current flowing across the first and second output terminals in dependence upon a determination of whether the potential of said first signal is greater than the potential of said second input signal to shorten a discharging time of said operational amplifier,
• wherein the generation and the grounding of the current flowing across the first and second output terminals improves the slew rate of the output signal at said second output terminal.

An amplifier circuit for a semiconductor memory device, comprising:

• differential amplifier means for generating difference signals being a function of differences between first input signals and second input signals received at a first input and a second input, respectively;
• a first pull-up transistor having a first pull-up transistor gate receiving said difference signals and a first pull-up transistor channel connected between a power voltage node and a first output node;
• a first pull-down transistor having a first pull-down transistor channel connected between said first output node and a ground voltage node;
• a second pull-up transistor having a second pull-up transistor gate receiving said difference signals and a second pull-up transistor channel connected between said power voltage node and a second output node;
• a second pull-down transistor having a second pull-down transistor channel connected between said ground voltage node and said second output node;
• a resistive path connected between said first output node and said second output node;
• a third pull-up transistor having a third pull-up transistor gate connected said first output node and a third pull-up transistor channel connected between said power voltage node and said second output node;
• and
• a third pull-down transistor having a third pull-down transistor gate connected to said first output node and a third pull-down transistor channel connected between said ground voltage node and said second output node;
• wherein a conductive type of said first pull-up transistor, said second pull-up transistor, and said third pull-down transistor is opposite to a conductive type of said first pull-down transistor, said second pull-down transistor, and said third pull-up transistor.