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AssigneeIntel Corporation
InventorsAdrian Carbine, Frank S. Smith
Estimating the term…
An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.
In an instruction sequencer including an alias register set (116), a microcode translation ROM (122) that stores a microcode flow which implements a macroinstruction, and a machine bus (110), said alias register set including a current alias register, said macroinstruction including an assembler mnemonic and an operand, a method comprising the steps of:
Dependencies are inferred from the claim text.