Processor controlled command port architecture for flash memory

An electrically erasable and electrically programmable read-only memory device fabricated on a single silicon substrate, comprising:

• (A) a memory array;
• (B) circuitry means coupled to the memory array for performing a memory operation with respect to the memory array, wherein the circuitry means can receive from an external processor an address via a plurality of address inputs, and data to be stored in the memory array via a plurality of data pins, wherein the circuitry means can also supply data stored in the memory array to the external processor via the data pins;
• and
• (C) command controller means coupled to the circuitry means for receiving a command from the external processor via the data pins and for generating predetermined control signals to the circuitry means in accordance with the command received for controlling the circuitry means to perform the memory operation, wherein the command controller means further comprises.
• (i) command and state register means for storing the command and for tracking a sequence associated with the memory operation;
• (ii) clock generation means for generating timing signals to (1) the circuitry means and (2) the command and state register means for controlling the latching of the address and the data to the circuitry means and the latching of the command to the command and state register means;
• and
• (iii) state decoder means coupled to the command and state register means for decoding the command received in the command and state register means to generate the predetermined control signals to the circuitry means.