US 5,222,030 A · Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof

Abstract

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

Claims23

Dependent claims

In an ECAD system, a method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:

entering on an ECAD system a specification for a design of desired behavior of a device, including high-level timing goals, in a high level, behavior-oriented language;
on the ECAD system, iteratively simulating and changing the design of the device at the behavioral-level until the desired behavior is obtained;
on the ECAD system, partitioning the design of the device into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals, and
on the ECAD system, directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design.

1 more element

In an ECAD system, a method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:

(1) entering on an ECAD system a specification for an entire design of desired behavior of a device, including high-level timing goals, in a high-level, behavior-oriented language;
(2) on the ECAD system, deriving a functional description from the specification, including intended functionality;
(2.5) on the ECAD system, verifying the correctness of the intended functionality of the functional description;
(3) on the ECAD system, partitioning the functional description into a partitioned design having separate modules;
(4) on the ECAD system, describing the modules, and imposing on each module a set of timing and area constraints;
(5) on the ECAD system, reconstructing the partitioned design, and examining and verifying the partitioned design, to provide an RTL description of the entire design;
(6) on the ECAD system, verifying architectural decisions that were made during partitioning, and examining their impact on the functionality and performance of the entire design;
(7) on the ECAD system, providing a target technology library for the modules;
(8) on the ECAD system, mapping the design is mapped into the target technology;
(9) on the ECAD system, providing a gate-level, technology-dependent structural descriptions of the modules;
(10) on the ECAD system, verify the correctness of the structural descriptions of the modules against their intended functionality;
(11) on the ECAD system, associating specified timing and area constraints on the structural description of the modules;
(12) on the ECAD system, modifying the structural descriptions of the modules so that their area and timing characteristics comply with the specified constraints;
(13) on the ECAD system, deriving optimized structural description of the modules from the modified structural descriptions;
(14) on the ECAD system, examining the impact of the optimized structural descriptions of the modules on the entire design;
(15) on the ECAD system, deriving a high level module, from the optimized structural descriptions of the modules, wherein the high level module describes the interaction and connectivity between the modules, and creating higher level modules hierarchically from high level modules until the entire design is described in a highest level module;
(16) on the ECAD system, composing the optimized structural descriptions of the modules are composed (see step 5) together to implement the intended functionality of the highest level module;
(17) in the ECAD system, performing floor-planning for the modules, and determining more accurate intra-block and interblock delays;
(17.5) in the ECAD system, back-annotating the delays into the structural descriptions of the modules;
and
(18) in the ECAD system, further modifying the structural descriptions of the modules so that their area and timing characteristics comply with global constraints.

18 more elements

Dependencies are inferred from the claim text.

Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof

Life of this patent

Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof

Life of this patent

Abstract

Claims23