# US 5,221,865 A · Programmable input/output buffer circuit with test capability

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- Number: US 5,221,865 A
- Document ID: US5221865A
- Status: Granted
- Kind: A
- Application number: 07/718,677
- Filed: 1991-06-21
- Granted: 1993-06-22
- Earliest claimed: 1991-06-21
- Assignees: Crosspoint Solutions, Inc.
- Inventors: Christopher E. Phillips; Michael G. Ahrens; Joseph G. Nolan, III; Laurence H. Cooke
- Web page: https://patentgrep.com/patent/US5221865A

## CPC

- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H03K 19/00361: {in field effect transistor circuits}
- H03K 19/018585: {programmable}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

## Claims

### Claim 1

In an integrated circuit having system logic with programmable elements, decoding logic coupled to said programming elements for addressing said programming elements, a plurality of input/output buffer circuits for passing signals between said system logic and the exterior of said integrated circuit through input/output terminals, each input/output buffer circuit comprising
an output driver stage having an input terminal, and an output terminal connected to an input/output terminal;
a plurality of cells, each cell having a first multiplexer, a first means connected to an output terminal of said first multiplexer for storing a signal from said first multiplexer, a second means connected to an output terminal of said first storing means for storing a signal from said first storing means, and a second multiplexer connected to an output terminal of said second storing means, at least one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and at least one of said multiplexers of said plurality of said cells connected to said input/output terminal and to said system logic for signals from said input/output terminal to said system logic, said cells connected to each other and cells of other input/output buffer circuits from an output terminal of a first storing means of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through said cells to test said system logic;
control lines connected to said output terminals of said second storing means of said cells and to said decoding logic coupled to said programming elements;
whereby said programming elements can be addressed for programming by serially scanning control signals through said cells.

### Claim 2 (depends on 1)

The input/output buffer circuit as in claim 1 wherein said system logic comprises a field programmable logic array.

### Claim 3 (depends on 2)

The input/output buffer circuit as in claim 2 wherein said programmable elements comprise antifuses.

### Claim 4 (depends on 1)

The input/output buffer circuit as in claim 1 wherein a first one of said cells has said at least one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and a second one of said cells has said at least one of said multiplexers of said plurality of said cells connected to said input/output terminal and to said system logic for signals from said input/output terminal to said system logic.

### Claim 5

In an integrated circuit having system logic, a plurality of input/output buffer circuits for passing signals between said system logic and the exterior of said integrated circuit through input/output terminals, each input/output buffer circuit comprising
an output driver stage having an input terminal, and an output terminal connected to an input/output terminal;
a plurality of cells, each cell having a first multiplexer, a first means connected to an output terminal of said first multiplexer for storing a signal from said first multiplexer, a second means connected to an output terminal of said first storing means for storing a signal from said first storing means and a second multiplexer connected to an output terminal of said second storing means, at least one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and at least one of said multiplexers of said plurality of said cells connected to said input/output terminal and to said system logic for signals from said input/output terminal to said system logic, said cells connected to each other and cells of other input/output buffer circuits from an output terminal of a first storing means of one cell to a first input of a first multiplexer of another cell for serial scanning of signals through said cells to test said system logic;
at least one signal storage element connected to said output driver stage for controlling the drive characteristics of said output driver stage responsive to a logic signal stored in said storage element;
a decoder for addressing said signal storage element for storing a logic signal in said storage element;
control lines connected to said output terminals of said second storing means of said cells and to said decoder;
whereby said programming elements can be addressed for storing a logic signal therein to control the drive characteristics of said output driver stage by serially scanning control signals through said cells.

### Claim 6 (depends on 5)

The input-output buffer circuit as in claim 5 wherein said output driver stage has means for controlling the amount of drive current responsive to said at least one signal storage element.

### Claim 7 (depends on 5)

The input-output buffer circuit as in claim 5 wherein said output driver stage has means for controlling the slew rate responsive to at least one signal storage element.

### Claim 8 (depends on 5)

The input/output buffer circuit as in claim 5 wherein at least one signal storage element comprises a field programmable element.

### Claim 9 (depends on 5)

The input/output buffer circuit as in claim 5 wherein said storage element comprises a programmable element and a logic signal is stored in said element by programming said element.

### Claim 10 (depends on 5)

The input/output buffer circuit as in claim 5 wherein said storage element comprises a memory circuit and a logic signal is stored in said circuit by reading in said logic signal into said circuit.

### Claim 11 (depends on 5)

The input/output buffer circuit as in claim 5 wherein a first one of said cells has said at least one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and a second one of said cells has said at least one of said multiplexers of said plurality of said cells connected to said input/output terminal and to said system logic for signals from said input/output terminal to said system logic.

### Claim 12

In an integrated circuit having system logic, a plurality if input/output buffer circuits for passing signals between said system logic and the exterior of said integrated circuit through input/output terminals, each input/output buffer circuit comprising
an output driver stage having an input terminal, and an output terminal connected to an input/output terminal;
a plurality of cells, each cell having a first multiplexer, a first means connected to an output terminal of said first multiplexer for storing a signal from said first multiplexer, a second means connected to an output terminal of said first storing means for storing a signal from said first storing means and a second multiplexer connected to an output terminal of said second storing means, one of said multiplexers of said plurality of cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, said cells connected to each other and cells of other input/output buffer circuits from an output terminal of first storing means of one cell to a first input of a first multiplexer of another cell for serial scanning of signals through said cells to test said system logic;
one of said cells having an input terminal of a multiplexer connected to said input/output terminal, an output terminal of said multiplexer connected to the system logic of said integrated circuit for signals from said input/output terminal to said system logic, said multiplexer having means for selecting an operating range of signals from said input/output terminal;
at least one signal storage element connected to said selecting means so that said selecting means selects an operating range of signals from said input/output terminal responsive to a logic signal stored in said storage element;
decoding logic for addressing said signal storage element for storing a logic signal in said storage element;
control lines connected to said output terminals of said second storing means of said cells and to said decoding logic;
whereby said programming elements can be addressed for storing a logic signal therein to control said operating range of signals from said input/output terminal by serially scanning control signals through said cells.

### Claim 13 (depends on 12)

The input/output buffer circuit as in claim 12 wherein said operating range of signals is a voltage range of input signals on said input/output terminal.

### Claim 14 (depends on 12)

The input/output buffer circuit as in claim 12 wherein said storage element comprises a programmable element and a logic signal is stored in said element by programming said element.

### Claim 15 (depends on 12)

The input/output buffer circuit as in claim 12 wherein said storage element comprises a memory circuit and a logic signal is stored in said circuit by reading in said logic signal into said circuit.

### Claim 16 (depends on 12)

The input/output buffer circuit as in claim 12 wherein
a first one of said cells has said one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and
a second one of said cells has said input terminal of a multiplexer connected to said input/output terminal, an output terminal of said multiplexer connected to the system logic of said integrated circuit for signals from said input/output terminal to said system logic.

### Claim 17 (depends on 16)

The input/output buffer circuit as in claim 16 wherein said multiplexer of said one of said cells comprises said second multiplexer of said cell.

### Claim 18

In an integrated circuit having system logic, a plurality of input/output buffer circuits for passing signals between said system logic and the exterior of said integrated circuit through input/output terminals, each input/output buffer circuit comprising
an output driver stage having an input terminal, and an output terminal connected to an input/output terminal, and means for selecting drive characteristics of said stage;
a plurality of cells, each cell having a first multiplexer, a first means connected to an output terminal of said first multiplexer for storing a signal from said first multiplexer, a second means connected to an output terminal of said first storing means for storing a signal from said first storing means, and a second multiplexer connected to an output terminal of said second storing means, one of said multiplexers of said plurality of cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, said cells connected to each other and cells of other input/output buffer circuits from an output terminal of first storing means of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through said cells to test said system logic;
one of said cells having an input terminal of a multiplexer connected to said input/output terminal, an output terminal of said multiplexer connected to said system logic of said integrated circuit for signals from said input/output terminal to said system logic;
a plurality of signal storage elements connected to said multiplexer of said one cell for selecting an operating range of signals from said input/output terminal and to said output driver stage for selecting the drive characteristics of said output driver stage responsive to logic signals stored in said signal storage elements;
decoding logic for addressing said signal storage element for storing logic signals in said storage elements; and
control lines connected to said output terminals of said second storing means of said cells and to said decoding logic coupled to said signal storage elements;
whereby said signal storage elements can be addressed for storing logic signals therein to select said operating range for signals from said input/output terminal and said drive characteristics of said output driver stage by serially scanning control signals through said cells.

### Claim 19 (depends on 18)

The input-output buffer circuit as in claim 18 wherein said output driver stage selecting means includes means for controlling the amount of drive current responsive to said at least one signal storage element.

### Claim 20 (depends on 18)

The input-output buffer circuit as in claim 18 wherein said output driver stage selecting means includes means for controlling the slew rate responsive to at least one signal storage element.

### Claim 21 (depends on 18)

The input-output buffer circuit as in claim 18 wherein said output driver stage has means for controlling the logic state of said output driver stage responsive to at least one signal storage element whereby said output driver stage can operate as an open source or open drain.

### Claim 22 (depends on 18)

The input/output buffer circuit as in claim 18 wherein said operating range of signals is a voltage range of input signals on said input/output terminal.

### Claim 23 (depends on 18)

The input/output buffer circuit as in claim 18 wherein said signal storage elements comprises field programmable elements.

### Claim 24 (depends on 18)

The input/output buffer circuit as in claim 18 wherein said storage elements comprise a programmable element and a logic signal is stored in said element by programming said element.

### Claim 25 (depends on 18)

The input/output buffer circuit as in claim 18 wherein said storage element comprises a memory circuit and a logic signal is stored in said circuit by reading in said logic signal into said circuit.

### Claim 26 (depends on 18)

The input/output buffer circuit as in claim 18 wherein
a first one of said cells has said one of said multiplexers of said plurality of said cells connected to said system logic and to said output driver stage input terminal for signals from said system logic to said output driver stage, and
a second one of said cells has said input terminal of a multiplexer connected to said input/output terminal, an output terminal of said multiplexer connected to said system logic of said integrated circuit for signals from said input/output terminal to said system logic.

### Claim 27 (depends on 26)

The input/output buffer circuit as in claim 26 wherein said multiplexer of said one of said cells comprises said second multiplexer of said cell.

### Claim 28

In an integrated circuit having system logic, a plurality of input/output buffer circuits for passing signals between said system logic and the exterior of said integrated circuit through input/output terminals, each input/output buffer circuit comprising
an output driver stage having an input terminal, and an output terminal connected to an input/output terminal;
a plurality of cells, each cell having a first multiplexer, a first means connected to an output terminal of said first multiplexer for storing a signal from said first multiplexer, a second means connected to an output terminal of said first storing means for storing a signal from said first storing means and a second multiplexer connected to an output terminal of said second storing means, said cells connected to each other and cells of other input/output buffer circuits from an output terminal of a first storing means of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through said cells to test said system logic;
a first one of said cells having an input terminal of a second multiplexer connected to the system logic of said integrated circuit, and an output terminal of said second multiplexer connected to said input terminal of said output driver stage for signals from said system logic to said output driver stage, and a second input terminal of a first multiplexer connected to a first node of said integrated circuit; and
a second one of said cells having an input terminal of a second multiplexer connected to said input/output terminal, an output terminal of said second multiplexer connected to said system logic for signals from said input/output terminal to said system logic, a second input terminal of a first multiplexer connected to said output terminal of said second multiplexer, and a third input terminal of said first multiplexer connected to a second node of said integrated circuit;
whereby signals can be introduced into said cells through said second input terminal of said first multiplexer of said first cell and said third input terminal of said first multiplexer of said second cell.

### Claim 29 (depends on 28)

The input/output buffer circuits as in claim 28 wherein said first and second nodes are in said system logic of said integrated circuit.

### Claim 30 (depends on 29)

The input/output buffer circuits as in claim 29 wherein system logic comprises a field programmable logic array and said first and second nodes have logic states responsive to the programming of said field programmable logic array.

### Claim 31 (depends on 28)

The input/output buffer circuits as in claim 28 further comprising a third input terminals of said first multiplexer of said first cell and a fourth input of said first multiplexer of said second cell, said third and fourth input terminals connected to said system logic of said integrated circuit whereby signals can be introduced into said cells through said third and fourth terminals.

### Claim 32 (depends on 31)

The input/output buffer circuits as in claim 31 further comprising a fourth input terminal of said first multiplexer of said first cell connected to said input terminal of said second multiplexer.

### Claim 33 (depends on 28)

The input/output buffer circuits as in claim 28 further comprising signal lines connected from each output terminal of second storing means of said first and second cells to said system logic of said integrated circuit whereby signals in said second storing means in said first and second cells may be passed into said system logic.

### Claim 34 (depends on 33)

The input/output buffer circuits as in claim 33 wherein said system logic comprises elements programmable by said signals in said second storing means in said first and second cells.

### Claim 35 (depends on 33)

The input/output buffer circuits as in claim 33 further comprising a programming unit, said programming unit connected to said output driver stage for controlling the drive characteristics of said output driver stage.

### Claim 36 (depends on 35)

The input/output buffer circuits as in claim 35 wherein said output driver stage has means for controlling the amount of drive current responsive to said programming unit.

### Claim 37 (depends on 35)

The input/output buffer circuits as in claim 35 wherein said output driver stage has means for controlling the slew rate responsive to said programming unit.

### Claim 38 (depends on 35)

The input/output buffer circuits as in claim 35 wherein said output driver stage has means for controlling the logic state of said output driver stage responsive to said programming unit whereby said output driver stage can operate as an open source or open drain.

### Claim 39 (depends on 35)

The input/output buffer circuits as in claim 35 wherein said signal lines from each output terminal of second storing means are coupled to said programming unit for programming said unit.

### Claim 40 (depends on 39)

The input/output buffer circuits as in claim 39 further comprising a decoding unit connected between said signal lines and said programming unit, said decoding unit generating control signals responsive to signals upon said signal lines for programming said unit.

### Claim 41 (depends on 39)

The input/output buffer circuits as in claim 39 wherein said system logic comprises elements programmable by said signals in said second storing means in said first and second cells.

### Claim 42 (depends on 39)

The input/output buffer circuits as in claim 39 wherein said first and second nodes are in said system logic of said integrated circuit.

### Claim 43 (depends on 42)

The input/output buffer circuits as in claim 42 wherein system logic comprises a field programmable logic array and said first and second nodes have logic states responsive to the programming of said field programmable logic array.