Semiconductor device having a pad array carrier package

A semiconductor device having a plastic pad array carrier package comprising:

• an organic polymer substrate having a die attach surface and a package mounting surface;
• an electronic component mounted on the die attach surface having a plurality of bonding pads on a face thereof;
• a first plurality of lead traces on the die attach surface each having an inner bonding area adjacent to the electronic component;
• electrical connections between the bonding pads on the electronic component and the inner bonding area of the first plurality of lead traces;
• a second plurality of lead traces on the package mounting surface electrically coupled to the first plurality of lead traces by a plurality of vias in the substrate, each via located at a predetermined distance from the corresponding bonding pad such that the signal transmission through the first and second plurality of lead traces maximized;
• a plurality of terminal solder pads on the package mounting surface which are displayed away from the vias;
• a solder mask overlying the package mounting surface and a portion of the terminal solder pads;
• and
• protection means overlying at least the electronic component and the electrical connections.

A semiconductor device having a plastic pad array carrier package comprising:

• a carrier substrate having a die attach surface and package mounting surface, the package mounting surface including a component mounting area;
• a plurality of irregularly spaced electrical vias in the carrier substrate extending from the die attach surface to the mounting surface;
• means for attaching an external element extending from the die attach surface to the component mounting area on the package mounting surface;
• an electronic component mounting on the die attach surface having a plurality of bonding pads of a face thereof;
• a first plurality of lead traces on the die attach surface each having an inner bonding area adjacent to the electronic component and each extending to an individual electrical via;
• electrical connections between the bonding pads on the electronic component and the inner bonding areas of the first plurality of lead traces;
• a plating layer overlying a surface of the electrical vias;
• a second plurality of lead traces on the package mounting surface electrically connected to the first plurality of lead traces by the plating layer and extending from the electrical vias to a plurality of regularly spaced terminal solder pads which are displaced away from the vias;
• a plurality of solder balls which are displaced away from the vias and are bonded to the terminal solder pads;
• a solder mask overlying the package mounting surface and a portion of the terminal solder pads;
• and
• a molded plastic package body overlying at least the electronic component and the electrical connections.

A semiconductor device having a pad array carrier package comprising:

• a carrier substrate having a die attach surface opposite a package mounting surface,
• the package mounting surface partitioned in a periodic array with locations defined at selected positions in the array and terminal solder pads located at a plurality of the locations, and
• the die attach surface partitioned in an a-periodic array with a plurality of via holes located at positions in the a-periodic array;
• an electronic component mounted on the die attach surface and having a plurality of bonding pads arrayed on a face thereof;
• a first plurality of lead traces overlying the die attach surface wherein each lead trace extends from a position proximate a selected bonding pad to a predetermined via;
• and
• a second plurality of lead traces overlying the package mounting surface wherein each lead trace extends from one of the plurality of vias to a selected solder pad.

A semiconductor device comprising:

• an electronic component having a plurality of bonding pads on a face thereof;
• a carrier substrate having a die attach surface opposite a package mounting surface, wherein the package mounting surface is partitioned in a periodic array with user defined locations at selected positions in the array and terminal solder pads located at a plurality of the locations;
• a first plurality of lead traces overlying the die attach surface, each trace electrically connected to a selected bonding pad on the electronic component;
• a second plurality of lead traces overlying the package mounting surface;
• and
• a plurality of vias in the carrier substrate electrically coupling the first and second plurality of lead traces,
• wherein each via is displaced away from a terminal solder pad, and
• wherein each via is located at a predetermined position such that the signal inductance between the bonding pad and the terminal solder pad is minimized.

A semiconductor device having a pad array carrier package for attachment to a package mounting substrate comprising:

• a flexible carrier substrate having a die attach surface opposite a package mounting surface, the substrate having a coefficient of thermal expansion substantially the same as the package mounting substrate;
• an electronic component mounted on the die attach surface;
• a plurality of vias in the carrier substrate, each via located at a selected position on the die attach surface, wherein the distance between the electronic component and the selected position varies such that signal transmission to and from the electronic component is optimized;
• a first plurality of lead traces overlying the die attach surface, wherein each lead trace is connected to a selected via and electrically coupled to the electronic component;
• an array of terminal solder pads on the package mounting surface displaced away from the vias;
• a second plurality of lead traces overlying the package mounting surface, wherein each trace connects one of the plurality of terminal solder pads to one of the first plurality of lead traces through the selected via;
• compliant solder balls joined to the terminal solder pads and arranged so as to align with and contact selected bonding sites on the package mounting substrate;
• a moulded package body overlying at least the electronic component and a portion of the first plurality of lead traces proximate the electronic component.

A semiconductor device having a flexible pad array carrier package for mounting on a mounting substrate comprising:

• a single layer substrate having a die attach surface opposite a package mounting surface, the single layer substrate having a coefficient of thermal expansion substantially the same as the mounting substrate;
• a plurality of vias extending through the carrier substrate from the die attach surface to the package mounting surface;
• first lead traces overlying the die attach surface, wherein each lead trace is connected to a selected via;
• an electronic component mounted on the die attach surface and electrically connected to the first plurality of lead traces;
• an array of terminal solder pads on the package mounting surface and displaced away from the vias;
• second lead traces on the package mounting surface connected to the vias and extending to the terminal solder pads;
• and
• a moulded package body overlying at least the electronic component and a portion of the first lead traces proximate the electronic component.