Self-scanning code reading device

A bar code reading device, comprising:

• means for receiving a generating clock signals;
• a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal;
• edge detecting means receiving in each of said repeated scans said electrical signal for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal;
• counter means receiving in each of said repeated scans said clock signals and said edge detection signal for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal;
• decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal, for detecting a bar code whenever a subset of said series of counts received demarcates bar code data, for decoding said bar code detected, in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code detected, for providing a decoded value of said bar code and asserting a successful decode signal;
• first memory means receiving said decoded value from said decoding means and said successful decode signal for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means;
• second memory means receiving a first control signal and said first output value of said first memory means for storing said first output value when said first control signal is received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means;
• comparator means, receiving said first output value and said second output values value, for comparing said first output value and said second output values value, said comparator means asserting said first control signal when said first output value and said second output values value are different, said comparator means asserting a second control signal when said first output value and said second output values value are the same;
• and
• output means, receiving each decoded value of said decoding means and said first and second control signals, for outputting the decoded value of said decoding means when said first control signal is asserted and for inhibiting output of said decoded value when said second control signal is asserted.

A bar code reading device, comprising:

• means for generating clock signals;
• a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal;
• edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal;
• first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal;
• decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal, for detecting a bar code scan whenever a subset of said series of counts received demarcates bar code data, for decoding said bar code detected, in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal;
• first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the value stored in said first memory means;
• second memory means receiving an external reset signal, first and second control signals, and said first output value for storing said first output value when said first control signal is received in an asserted state, unless said second control signal is received in an asserted state after initialization and prior to receiving said asserted first control signal, said second memory means being initialized when receiving said external reset signal in an asserted state, and for providing a second output value representing the value stored in said second memory means;
• comparator means, receiving said first output value and said second output value, for comparing said first output value and said second output value, said comparator means asserting said first control signal when said first output value and said second output value are different, said comparator means asserting a second control signal when said first output value and said second output value are the same;
• second counter means, receiving said second control signal, a third control signal and said external reset signal, for providing as an assertion count the number of times said second control signal is asserted after either said external reset signal or said third control signal is received in an asserted state;
• judging means for asserting said third control signal when said assertion count is not less than said predetermined number and asserting a fourth control signal when said assertion count is less than said predetermined number;
• and
• output means, receiving each decoded value of said decoding means and aid third and fourth control signals, for outputting said decoded value when said third control signal is asserted and for inhibiting output of said decoded value when said fourth control signal is asserted.

A bar code reading device, comprising:

• means for generating clock signals;
• a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal;
• edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal;
• first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal;
• start-stop means, receiving a reset signal, said edge detection signal and said series of counts, for detecting in each bar code scanned a pair of start and stop codes, said start-stop means is initialized to detect said start code when said reset signal is in an asserted state, said start-stop means asserting a code normal signal when both said start and stop codes are detected, and asserting said code fail signal when at least one of said start and stop codes is not detected;
• decoding means, receiving said code normal and code fail signals, said series of counts and said edge detection signal, for decoding said bar code in each detected bar code scan in accordance with said series of counts, said code normal and code fail signals and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal, and for asserting said reset signal whenever a decoding is incorrectly executed;
• first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means;
• second memory means, receiving first and second control signals and said output value of said first memory means, for storing said output value when said first control signal is received in an asserted state, said second memory means cleared by said second control signal received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means;
• comparator means, receiving said first output value and said second output value, for comparing said first output value and said second output value, said comparator means asserting a third control signal when said first output value and aid second output value are different, said comparator means asserting a fourth control signal when said first output value and said second output value are the same;
• switch means for receiving said second, third and fourth control signals for providing said third signal as said first control signal from the time said second control signal is received in an asserted state to the time said fourth control signal is received in an asserted state;
• second counter means, receiving said second, third, and fourth control signals and a fifth control signals, for providing an assertion count equal to the number of times said fourth control signal is received in an asserted state since the last time said second control signal is received in an asserted state, said assertion count is initialized to zero when either said second control signal or said fifth control signal is received in an asserted state;
• judging means, receiving said assertion count, for asserting said fifth control signal when said second count is not less than a predetermined number, and asserting a sixth control signal when said assertion count is less than said predetermined number;
• and
• output means, receiving each decoded value of said decoding means and said fifth and sixth control signals, for outputting said decoded value when said fifth control signal is asserted and for inhibiting output of said decoded value when said sixth control signal is asserted.

A bar code reading device, comprising:

• means for generating clock signals;
• a photoelectric converting means for performing repeated scans on a bar code presented to said reading device and converting edges between the bars and spaces in each of said repeated scans into a set of transitions in an electrical signal;
• edge detecting means, receiving in each of said repeated scans said electrical signal, for detecting said transitions and for providing, for every transition detected in said electrical signal, a corresponding transition in an edge detection signal;
• first counter means, receiving in each of said repeated scans said clock signals and said edge detection signal, for providing a series of counts, each count provided in accordance with the number of said clock signals received between successive transitions of said edge detection signal;
• decoding means, receiving in each of said repeated scans said series of counts and said edge detection signal for detecting that a bar code is scanned whenever a subset of said series of counts received demarcates bar code data, for decoding, in each bar code scanned, said bar code detected in accordance with said series of counts and said edge detection signal, and upon successfully decoding said bar code, for providing a decoded value of said bar code and asserting a successful decode signal;
• first memory means, receiving said decoded value from said decoding means and said successful decode signal, for storing said decoded value received when said successful decode signal is asserted, said first memory means providing a first output value representing the stored content of said first memory means;
• second memory means, receiving a first control signal and said output value of said first memory means, for storing said output value when said first control signal is received in an asserted state, said second memory means providing a second output value representing the stored content of said second memory means;
• comparator means, receiving said first output value and said output value, for comparing said first output value and said second output value, said comparator means asserting said first control signal when said first output value and said second output value are different, said comparator means asserting a second control signal when said first output value and said second output value are the same;
• second counter means, receiving said first and second control signals, for providing an assertion count equal to the number of times said second control signal is received in an asserted state since the last time said first control signal is received in an asserted state;
• judging means, receiving said assertion count, for asserting a third control signal when said second count is not less than a predetermined number, and asserting a fourth control signal when said assertion count is less than said predetermined number;
• and
• output means, receiving each decoded value of said decoded means and said third and fourth control signals, for outputting said decoded value when said third signal is asserted and for inhibiting output of said decoded value when said fourth control signal is asserted.