Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency
AssigneeVLSI Technology, Inc.
InventorsCreigton S. Asato, Suresh K. B. Dholakia, Christoph Ditzen
Life of this patent
Estimating the term…
Abstract
According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as: D.sub.s =D.sub.b N.sub.b +C where D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
Claims10
A method for locating pipelining stages in a multi-stage datapath element including a plurality of multiple-bit functional stages, comprising machine execute steps of:
- a) for each functional stage of a multi-stage datapath element, estimating a stage delay time through the functional stage as a function of a delay for communication of bits within the stage, a total number of bits in the datapath element, and a constant;
- and
- b) with an automated integrated circuit design system locating pipelining stages between functional stages within the multi-stage datapath element in accordance with the estimated stage delay times.
A method for locating pipelining stages in a multi-stage datapath element with an automated integrated circuit design system comprising machine execute steps of:
- a) for each functional stage of the datapath element, estimating with said automated design system a stage delay time in accordance with:
- D.sub.s =D.sub.b N.sub.b +C
- where D.sub.s is the estimated stage delay, D.sub.b is a delay time for communication of bits within each functional stage, N.sub.b is the number of bits in each functional stage in the datapath element, and C is a constant;
- b) calculating locations for pipelining stage placement positions as a function of each of said estimated stage delay;
- and
- c) with said automated integrated circuit design system, locating pipelining stages at the calculated locations within the multi-stage datapath element.
Dependencies are inferred from the claim text.