System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory

An electronic processor in which data is cyclically processed, comprising:

• a semiconductor memory arranged and adapted to be read from and written to, including
• an array of memory cells arranged in rows and columns identifying memory locations of said semiconductor memory,
• each of said memory locations having a unique address,
• said array divided into a first half containing memory locations with even numbered addresses and a second half containing memory locations with odd numbered addresses,
• signal generating means electrically connected to said semiconductor memory for generating electrical shift signals to increment the addresses of said memory locations through a sequence of consecutively higher numbered addresses,
• selecting means for selecting an address designating a memory location from among the memory locations from which data is to be read,
• access means responsive to the selection of an address for reading data from the memory location designated by said selected address in one of said first and second halves during a predetermined instruction processing cycle of said electronic processor, and
• shift means responsive to an electrical shift signal generated by said signal generating means in response to the reading of data by said access means from said designated memory location for automatically writing data read from said designated memory location into the memory location in the other of said first and second halves of said array designated by the next sequentially higher address relative to said selected address during the same said predetermined instruction processing cycle.