Improper writing prevention circuit and a memory device and a data processing device which include the circuit

A memory device, comprising:

• memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the states;
• source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage;
• storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register;
• a data bus operably connected to said memory means and said storage means;
• validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination;
• and
• state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals.

A memory device, comprising:

• memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates;
• a data bu adapted to supply data to said memory means;
• source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage;
• and
• an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, and state selection signal generating means for receiving said first control signal and data from said test register, for analyzing the data from said test register, and for generating a state selection signal to be applied to said sate selection terminal in a accordance with the value of said first control signal.

A data processing device, comprising:

• memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates;
• source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dependent on the value of the source voltage;
• storage means, including a test register, for receiving and storing reference data and for receiving and storing predetermined data, the reference data being stored in said test register;
• a data bus operably connected to said memory means and said storage means;
• validity check means, operably connected to said storage means, for performing a writing test which determines whether or not the reference data is consistent with the predetermined data, and for generating a second control signal having a value which is dependent on the determination;
• state selection means for receiving said first an second control signals from said source voltage detection means and said validity check means, respectively, and for producing a state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals;
• and
• a control block including microprocessor means for writing reference data into said first test register prior to an actual writing operation.

A data processing device, comprising:

• memory means having at least an active state in which data can be written to and read from said memory means, and a non-active state in which data stored in said memory means is maintained, said memory means including a state selection terminal for selecting one of the sates;
• a data bus adapted to supply data to said memory means;
• source voltage detection means for detecting a value of a source voltage and for generating a first control signal having a value which is dep3ndent on the value of the source voltage;
• an improper writing prevention circuit including a read and write test register adapted to receive data from said data bus, a decoder adapted to decode the data stored in said test register and to produce a second control signal having a value which is dependent on the decoding, and state selection control means for generating the state selection signal to be applied to said state selection terminal in accordance with the values of said first and second control signals;
• and
• a control block including microprocessor means for writing predetermined data into said read and write test register prior to an actual writing operation.