Small programmable array to the on-chip control store for microcode correction

In a microprocessor system having a register means for receiving a macroinstruction, a control store memory for storage and output of microinstructions associated with a macroinstruction, and a microsequencer means for producing a next address signal to address a next executable microinstruction, an apparatus for correcting one or more faulty microinstructions contained in said control store, said apparatus comprising:

• (a) a programmable detection circuit means coupled to said register means and programmed to detect a macroinstruction previously determined to have one or more faulty microinstructions associated therewith, said programmable detection circuit means outputting a decoder signal and a detection signal upon detection of said macroinstruction;
• (b) a first programmable memory array for receiving said decoder signal and programmed to contain a first error free microinstruction, said first memory array outputting said first error-free microinstruction for further processing in response to said decoder signal;
• (c) a second programmable memory array for receiving said next address signal and programmed to contain one or more error-free microinstructions corresponding to said faulty microinstructions contained in said control store, said second programmable memory array outputting said one or more error-free microinstructions for further processing in response to said next address signal;
• (d) selecting means responsive to said detection signal and said next address signal for selecting an error-free microinstruction output from one of said control store memory, said first programmable array and said second programmable array.