Asynchronous time division switching arrangement and a method of operating same

A method of operating an asynchronous time division multiplex switching arrangement comprising the steps of receiving input packets of data, by a serial to parallel converter, including routing information, in serial form;

• converting the packets of data to parallel form selecting data from the serial to parallel converter by a walking one sequencer;
• entering each packet of data in parallel form into an addressed location of a random access memory;
• drawing the address from the head of a first-in first-out queue of addresses of free locations in the memory where one or more separate FIFO output queuing means each associated with an output are provided to list in order of arrival the address location of input packets directed to said output, accessing the address when an address comes to the head of the queue;
• reading the packet of data from the random access memory into a parallel to serial converter;
• converting the packet of data to serial form;
• and serially delivering the packet of data to a required output.