Memory apparatus having flexibly designed memory capacity

A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words.times.D bits, the memory apparatus comprising:

• (N+J) memory units, each having a W words.times.B bits configuration and being equally divided into P element address areas, a.sub.1, a.sub.2, . . . , a.sub.p ;
• wherein
• D=2.sup.d, and d is a positive integer,
• W=2.sup.w, and w is a positive integer,
• B=2.sup.b, b is zero or a positive integer and b<d,
• J is a positive integer and J<N,
• N=D/B=2.sup.d-b, and
• P=N.multidot.L/J and P and L are positive integers;
• and
• wherein said W(1+J/N) words.times.D bits memory configuration is divided into (P+L) memory address areas A.sub.1, A.sub.2, . . . , A.sub.P+L, so that each memory address area comprises N element address areas, only one of which comes from a corresponding memory unit.

A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words.times.D bits, the memory apparatus comprising:

• (N+J) commercially available semiconductor memory units each having a W words.times.B bits configuration and wherein D>B and N is a fixed number representative of a number of memory units necessary for achieving a configuration having a data bus of D-bit wide and J is a flexible number less than N and representative of an additional number of memory units necessary for achieving said memory configuration of W(1+J/N) words.times.D bits;
• wherein each memory unit is divided into P memory element address areas, a.sub.1, a.sub.2, . . . , a.sub.p, each having W/P words, wherein P=N.multidot.L/J, L is a flexible number;
• and
• wherein said W(1+J/N) words.times.D bits memory configuration is divided into (P+L) memory address areas A.sub.1, A.sub.2, . . . , A.sub.P+L, so that each memory address area comprises an addressable set of N element address areas, only one of which comes from a corresponding memory unit, wherein L represents an additional number of memory address areas in said memory configuration attributable to J memory units.