Internal address determining device for semiconductor memory devices

An internal address determining device for a semiconductor memory device, comprising:

• an input section to which are input an external address strobe signal and an external address signal, said external address signal including an external row address signal and an external column address signal;
• first and second internal counters for storing addresses to be accessed in different operation modes;
• a first multiplexer for selecting and outputting one of the external row address signal input from the input section and an address signal stored in the first internal counter;
• a second multiplexer for selecting and outputting one of the external column address signal input from the input section and an address signal stored in the second internal counter;
• a timing circuit for controlling operation timing of said first and second multiplexers by generating one of first, second, third and fourth control signals in accordance with an operation mode of the semiconductor memory device, said first control signal controlling timing at which the external row address signal is accepted by the first multiplexer while said second control signal controlling timing at which the address signal stored in the first internal counter is accepted by the first multiplexer, and said third control signal controlling timing at which the external column address signal is accepted by the second multiplexer while said fourth control signal controlling timing at which the address signal stored in the second internal counter is accepted by the second multiplexer;
• a first latch circuit for latching output from said first multiplexer to output as an internal address to be accessed;
• and
• a second latch circuit for latching output from said second multiplexer to output as an internal address to be accessed.