Digital filter having a switching matrix and adders

A digital filter for producing an output signal based on an input signal and an intermediate signal, the intermediate signal comprising a plurality of delay signals, each of said delay signals of the intermediate signal having different delay times, the digital filter comprising:

• an input terminal for receiving the input signal;
• a serially connected tapped delay line connected to the input terminal, alternatingly comprising n taps and n-1 delay elements, each of the n-1 delay elements outputting one of the delay signals of the intermediate signal, each delay signal having a different delay time, the n taps providing the input signal and the n-1 delay signals to a switching circuit;
• the switching circuit comprising a plurality of switches arranged in a matrix having n columns and m rows, a switched input of each of the m switches of each of the n columns parallelly connected to one of the n taps for receiving one of the input signal and the n-1 delay signals as a switched input signal, the n switches of each of the m rows being serially connected, wherein each of the plurality of switches comprises the switched input, an adder connected to an output for outputting a summed signal, an unswitched input connected to the adder for inputting a summed signal from a serially upstream switch, and a switch element for selectively connecting one of the switched input signal and a predetermined signal to the adder;
• a multiplier circuit comprising m multipliers, each of the m multipliers associated with a corresponding one of the m rows for inputting the summed signal from a last one of the n switches of the corresponding row and outputting a multiplied signal;
• and
• an adder having m inputs for inputting and summing the multiplied signals of the m multipliers and outputting the output signal, wherein the switching circuit is controlled to selectively connect at least one of the taps to one of the m multipliers.

A digital filter for producing an output signal based on an signal, the output signal comprising a plurality of delay signals, each of said delay signals having different delay times, the digital filter comprising:

• an input terminal for receiving the input signal;
• a multiplier circuit comprising m multipliers, each of the m multipliers receiving the input signal and outputting a multiplied signal;
• a switching circuit comprising a plurality of switches arranged in a matrix having n columns and m rows, each of the plurality of switches having a switched input, an output for outputting an output signal and a switch element for selectively connecting the switched input to the output, the switched input of each of the n switches of each of the m rows connected in parallel to one of the m multipliers for receiving the multiplied signal of the one multiplier;
• and
• a serially connected delay line, alternatingly comprising n adders and n-1 delay elements, each of the n-1 delay elements outputting as a delay signal an input signal delayed by a same delay time, wherein each one of the n-1 delay elements receives a summed output signal from an upstream adder as an input signal and outputs the delay signal of the one delay element to a downstream adder,
• each one of the n adders is associated with one of the n column of the switching matrix and has n+1 inputs, each of the n+1 inputs being connected to one of an upstream delay element and the output of one of the m switches of said column for outputting a sum of the delay signal of the upstream delay element and the output signals of the m switches as the summed output signal of the one adder, the summed output of the nth adder being the output signal, and
• wherein the switching circuit is controlled to selectively connect at least one of the m multipliers to at least one of the n adders.

A digital filter for producing an output signal based on an input signal, the output signal comprising a plurality of delay signals, each of said delay signals having different total delay times, the digital filter comprising:

• an input terminal for receiving the input signal;
• a multiplier circuit comprising m multipliers, each of the m multipliers receiving the input signal and outputting a multiplied signal;
• a switching circuit comprising a plurality of switches arranged in a matrix having n columns and m rows wherein one of the m multipliers is associated with a corresponding one of the m rows, each of the plurality of switches comprising a first adder connected to an output for outputting a first summed signal, an unswitched input connected to the adder for inputting the first summed signal from a serially upstream switch, and a switched input for receiving a switched input signal and a switch element for selectively connecting one of the switched input signal and a predetermined signal to the adder, the n switches of each of the m rows parallel connected to one of the m multipliers for receiving the multiplied signal of the one multiplier as the switched input signal;
• and
• a serially connected delay line, alternatingly comprising n second adders and n-1 delay elements, each of the n-1 delay elements outputting a delay signal delayed by a same delay time,
• wherein each one of the n-1 delay elements inputs and delays by the same delay time a second summed output signal from an upstream second adder, the second summed output comprising at least one of a first summed output and at least one upstream delay signal, and outputs the delay signal of the one delay element, such that each at least one upstream delay signal is further delayed,
• each one of the n second adders is associated with a corresponding one of the n column of the switching matrix and has at least one of two inputs, a first input being connected to an upstream delay element and a second input being connected to the first summed output of a last switch of the corresponding column for outputting a sum of the delay signal and the first summed output signals as the second summed output signal of the one second adder, the second summed output of a last second adder being the output signal, and
• wherein the switching circuit is controlled to selectively connect at least one of the m multipliers to at least one of the n second adders.