Scan path generation with flip-flop rearrangement according to geometry of logic circuit

A scan path generation system for arranging a plurality of flip-flops of a logic circuit along a scan path, comprising:

• first scan path generation means for generating original scan path data which represents a sequence according to which said flip-flops would originally be connected in said scan path;
• placement means for placing said flip-flops on a two-dimensional plane according to said original scan path data;
• memory means for storing a sequence of said flip-flops which meets geometrical design requirements of said logic circuit;
• rearrangement means for rearranging said flip-flops placed on said two-dimensional plane according to said sequence stored in said memory means;
• and
• second scan path generation means for deriving from said rearranged flip-flops new scan path data representative of a new sequence according to which said flip-flops are to be newly connected in said scan path and replacing said original scan path data with said new scan path data.

A scan path generation system for arranging a plurality of flip-flops of a logic circuit along a scan path, comprising:

• first scan path generation means for deriving from logical connection data original scan path data which represents a sequence according to which said flip-flops would originally be connected in said scan path;
• storage means for storing said original scan path data and said logical connection data;
• placement means for placing said flip-flops and logic elements of said logic circuit on a two-dimensional plane according to said original scan path data and to said logical connection data stored in said storage means;
• table memory means for storing a sequence of said flip-flops which meets geometrical design requirements of said logic circuit;
• rearrangement means for rearranging said flip-flops placed on said two-dimensional plane according to said sequence stored in said table memory means;
• and
• second scan path generation means for deriving from said rearranged flip-flops new scan path data representative of a new sequence according to which said flip-flops are to be newly connected in said scan path and replacing said original scan path data stored in said storage means with said new scan path data.

A scan path generation method for arranging a plurality of flip-flops of a logic circuit along a scan path, comprising:

• a) placing said flip-flops on a two-dimensional plane according to original scan path data which represents a sequence according to which said flip-flops would originally be connected in said scan path;
• b) rearranging said flip-flops placed on said two-dimensional plane according to a sequence according to which said flip-flops would be connected in a pattern that meets geometrical design requirements of said logic circuit;
• and
• c) deriving from said rearranged flip-flops new scan path data representative of a new sequence according to which said flip-flops are to be newly connected in said scan path and replacing said original scan path data with said new scan path data.

A scan path generation method for arranging a plurality of flip-flops of a logic circuit along a scan path, comprising:

• a) mapping said flip-flops on an X-Y coordinate plane according to original scan path data which represents a sequence according to which said flip-flops would originally be connected in said scan path;
• b) rearranging said flip-flops placed on said plane according to a map which describes relationships between sequentially arranged values on an X coordinate of said plane and sequentially arranged values on a Y coordinate of said plane, said map meeting geometrical design requirement of said logic circuit;
• and
• c) deriving from said rearranged flip-flops new scan path data representative of a new sequence according to which said flip-flops are to be newly connected in said scan path and replacing said original scan path data with said new scan path data.