Circuit for code converting PCM codes

A code conversion circuit for converting a .mu.LawPCM code of 8-bits into a linear code, said conversion circuit comprising an inversion circuit coupled to receive an 8-bit signal of said .mu.LawPCM code and to output an 8-bit inverted code signal responsive thereto, means for giving a 6-bit signal which is obtained by adding a "1" bit to a less significant four bits of said 8-bit inverted code signal at a place which is lower than the least significant bit of said less significant four bits of said 8-bit inverted code signal by one bit and by adding another "1" bit at a place higher than the most significant bit of the less significant four bits of said 8-bit inverted code signal by one bit, a bit shift circuit means having a data input coupled to receive and shift the 6-bit signal in the most significant bit direction by an amount which is within a range from a 0 bit to 7 bits and which is determined by second to fourth significant bits of said 8-bit inverted code signal, said bit shift circuit means outputting the result of a shift in the form of a 13-bit signal, and a constant number addition circuit means coupled to receive said 13-bit signal for adding a predetermined number to said 13-bit signal, so that a 14-bit linear code is constituted of a 13-bit output of said addition circuit and the most significant bit of said 8-bit inverted code signal is added as a sign bit at a place higher than the most significant bit of the 13-bit output of said addition circuit by one bit.

A code conversion circuit for converting .mu.LawPCM code of 8 bits into a linear code, said conversion circuit comprising an inversion circuit for receiving an 8-bit signal of .mu.LawPCM code and for outputting an 8-bit inverted 8-bit inverted code signal, a bit shift circuit means having a data input connected to receive a 6-bit signal, means for obtaining said 6-bit signal by adding a "1" bit to less significant four bits of said 8-bit inverted code signal at a place which is lower than the least significant bit of said less significant four bits of said 8-bit inverted code signal by one bit and another "1" bit at a place which is higher than the most significant bit of the less significant four bits of said 8-bit inverted code signal by one bit, said bit shift circuit means operating to shift the received 6-bit signal in the most significant bit direction by an amount which is within a range of 0 to 7 bits and which is determined by second to fourth significant bits of said 8-bit inverted code signal, said bit shift circuit means outputting the result of a shift in the form of a 13-bit signal, and a constant number addition circuit means coupled to receive said 13-bit signal for adding a predetermined number to said 13-bit signal, and a one's complement circuit means for receiving a 13-bit output of said addition circuit and for outputting an exclusive-OR between said 13-bit output of said addition circuit and the most significant bit of said 8-bit inverted code signal, so that a 14-bit linear code is constituted of a 13-bit output of one's complement circuit and the most significant bit of said 8-bit inverted code signal added as a sign bit place higher than the most significant bit of the 13-bit output of said one's complement circuit by one bit.