Input buffer with reduced offset for operational amplifiers or the like
AssigneeAT&T Bell Laboratories
InventorsDouglas R. Frey, John W. Pierdomenico
Life of this patent
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Abstract
An amplifier circuit for use as a unity gain buffer or an input stage in a current-mode feedback amplifier. As a unity gain buffer, the circuit has very low output impedance and wide dynamic range while having low offset. As an input stage, the circuit has a very low impedance inverting input and a high impedance non-inverting input with wide dynamic range and low offset. The circuit has two mirror image halves, each half having four transistors of the same polarity type and a current mirror. Each half is biased by a current source, the sources having nearly identical current.
Claims9
In an integrated circuit, an amplifier having an input and an input/output terminal, characterized by:
- a first transistor, having a base, emitter, and a collector, the base coupling to the input of the amplifier;
- a second transistor, having a base, emitter, and a collector, connected as a diode and having two terminals, a first one of the two terminals coupling to the emitter of the first transistor;
- a third transistor, having a base, emitter, and a collector, connected as a diode and having two terminals, a first one of the two terminals coupling to a second one of the two terminals of the diode-connected second transistor;
- a fourth transistor, having a base, emitter, and a collector, the base connecting to a second one of the two terminals of the diode-connected third transistor, and the emitter connected to the input/output terminal;
- a current source coupling to the emitter of the first transistor;
- and
- a current mirror having an input and an output, the input coupling to the collector of the first transistor and the output coupling to the base of the fourth transistor.
Dependencies are inferred from the claim text.