Differential output, power, CMOS, operational amplifier

A power CMOS operational amplifier with a differential output having an intrinsically stable current absorption under rest conditions, and having two symmetrical branches, each branch of said amplifier comprising:

• an inverting input circuit electrically coupled to an input to generate an inverted amplified signal;
• a level shifting circuit electrically coupled to said inverted amplified signal to generate a shifted signal;
• a non-inverting amplifier circuit electrically coupled to said shifted signal to generate an amplified shifted signal;
• a CMOS power output circuit electrically coupled to said amplified shifted signal and to said shifted to generate an output signal;
• a frequency compensation circuit formed by a first capacitor connected between said output signal and said inverted amplified signal, and by a second capacitor connected between said output and said non-inverting amplifier circuit;
• a common mode feedback network formed by a first and second feedback capacitors connected in series with each other between the differential output terminals of the operational amplifier with the common node between said first and second feedback capacitors being connected to a common input on the operational amplifier;
• and
• a third and fourth feedback capacitors periodically connected in parallel to said first and second feedback capacitors, respectively, by means of a plurality of switches and alternately connected through said plurality of switches to a preset common node reference voltage, said common mode feedback network generating a voltage, in response to the voltage on said common mode input, to increase or decrease the voltage generated by said first and second inverting input circuits.

A power CMOS operational amplifier with a differential output having an intrinsically stable current absorption under rest conditions, said amplifier comprising:

• first and second inputs to the operational amplifier for the introduction of a differential input signal;
• first and second symmetrical branches for amplifying said differential input signal;
• first and second inverting input stages electrically coupled to said first and second inputs, respectively, to receive said differential input signal and to generate a first and second inverted amplified output signals;
• first and second level shifting stages, electrically coupled to said first and second inverted amplified output signals, respectively, to generate first and second shifted signals of the same polarity as said first and second inverted amplified output signals and shifted in level by a predetermined amount;
• first and second amplifier stages electrically coupled to said first and second shifted signals, respectively, to produce first and second amplified signals;
• first and second CMOS power stages each formed by a first and second pair of complementary MOS transistors, the first complementary MOS transistor of said first pair of complementary MOS transistors being electrically coupled to said first amplified signal, the second complementary MOS transistor of said first pair of complementary MOS transistors being electrically coupled to said first shifted signal, the first complementary MOS transistor of said second pair of complementary MOS transistors being electrically coupled to said second amplified signal, the second complementary MOS transistor of said second pair of complementary MOS transistors being electrically coupled to said second shifted signal, to produce a first and second power outputs, respectively;
• and
• first and second frequency compensation networks, electrically coupled to said first and second symmetrical branches, respectively, said first frequency compensation circuit formed by a first capacitor connected between said first power output and said first inverted amplified output signal, by a second capacitor connected between said first power output and said first amplifier stage, said second frequency compensation circuit formed by a third capacitor connected between said second power output and said second inverted amplified output signal, and by a fourth capacitor connected between said second power output and said second amplifier stage.