Power on reset circuit having hysteresis inverters

A power-on reset circuit responsive to a first power supply potential from a first power supply conductor and having an output for providing a reset signal after said first power supply potential reaches a threshold, comprising:

• first means responsive to said first power supply potential for developing a first reset signal having a first logic state when said first power supply potential is less than a first predetermined threshold, said first reset signal having a second logic state when said first power supply potential is greater than a second predetermined threshold;
• a first transistor having a gate, a drain and a source, said drain and gate receiving said first power supply potential;
• a second transistor having a gate, a drain and a source, said drain and gate being coupled together to said source of said first transistor;
• a third transistor having a gate, a drain and a source, said drain being coupled to said source of said second transistor;
• a first inverter circuit with hysteresis having an input coupled to said source of said third transistor at a first node and having an output at a second node;
• a second inverter having an input coupled to said second node and having an output;
• and
• a NOR gate having first and second input and an output, said first input receiving said first reset signal, said second input receiving said second reset signal, said output being coupled to said gate of said third transistor.

A power on reset circuit, comprising:

• first means responsive to a first power supply potential for developing a first reset signal when said first power supply potential is greater than a first predetermined threshold;
• second means responsive to said first power supply potential for developing a second reset signal when said first power supply potential is greater than a second predetermined threshold, said second means receiving said first reset signal to disable said second means until said first power supply potential reaches said first predetermined threshold;
• third means operating in response to an input clock signal for generating first and second clock signals having opposite phase;
• and
• a delay circuit having an input coupled for receiving said second reset signal and having first and second control inputs for receiving said first and second clock signals, said delay circuit providing a delayed second reset signal at an output following a predetermined number of cycles of said first and second clock signals.