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US 5,212,410 AGranted
Register circuit in which a stop current may be measured
AssigneeNEC Corporation
InventorRyuichi Sase
Life of this patent
Estimating the term…
Abstract
An output terminal of a register circuit in an LSI circuit such as a microcomputer, etc. is set to be a set state and is reset to be a reset state in accordance with set and reset signals and a clock-stop signal which is generated at a stop mode. A stop current is measured to flow between a predetermined node of the register circuit at the set state, and between the predetermined node and a power supply at the reset state.
Claims2
A register circuit, comprising:
- a parallel circuit of N and P channel type transistors connected between an input terminal and a first predetermined node, gates of said N and P channel type transistors being coupled to receive clock pulse and inverted clock pulse signals respectively;
- a feedback loop circuit of a transmission invertor and a feedback invertor connected between said first predetermined node and a second predetermined node;
- an output invertor connected between said second predetermined node and an output terminal;
- a first gate circuit coupled to receive a clock-stop signal and a register circuit-set signal to generate a first gate signal;
- a second gate circuit to receive said clock-stop signal and a register circuit-reset signal to generate a second gate signal;
- and
- a circuit for setting an output of said register circuit to a set state in responses to said first gate signal, and for resetting said output of said register circuit to a reset state in response said second gate signal.
4 more elements
Dependencies are inferred from the claim text.