US 5,212,402 A · Semiconductor device with integral decoupling capacitor

Abstract

A semiconductor device (10) has a decoupling capacitor (55) which is formed of a ground paddle (37), a dielectric element (57), and a power paddle (23). The power paddle is formed as a conductive element of a first TAB leadframe (12) and is contiguous with power leads (19). The first TAB leadframe also includes signal leads (16). The ground paddle is formed as a conductive element of a second TAB leadframe (14) and is contiguous with ground leads (36). The two leadframes are superimposed with one another to form the decoupling capacitor and to intersperse the ground leads with the power and signal leads. In one embodiment of the invention, power paddle (23) is raised above the leads to accommodate the dielectric element. The invention permits all power and all ground leads to be electrically coupled to the decoupling capacitor while keeping the decoupling capacitor very close to a semiconductor die (38).

Claims17

Dependent claims

A semiconductor device comprising:

a semiconductor die having a plurality of first voltage bond pads and a plurality of second voltage bond pads;
a first leadframe having a first voltage plane and a plurality of first voltage leads which are contiguous with the first voltage plane, the first voltage leads being electrically coupled to the plurality of first voltage bond pads of the semiconductor die;
a second leadframe having a second voltage plane and a plurality of second voltage leads which are contiguous with the second voltage plane, the second voltage leads being electrically coupled to the second voltage bond pads of the semiconductor die, the second leadframe being superimposed with the first leadframe such that second voltage plane overlies the first voltage plane, such that both the first and second voltage planes overlie the semiconductor die, and such that the first and second leadframes are electrically isolated from one another;
and
a dielectric element separating the first and second voltage planes to form a decoupling capacitor over the semiconductor die.

2 more elements

A method of fabricating a semiconductor device, comprising the steps of:

providing a semiconductor die having a plurality of first voltage bond pads and a plurality of second voltage bond pads;
providing a first leadframe having a first voltage plane formed of a conductive film and a plurality of first voltage leads which are contiguous with the first voltage plane, each first voltage lead having an inner lead portion;
providing a second leadframe having a second voltage plane and a plurality of second voltage leads which are contiguous with the second voltage plane, each second voltage lead having an inner lead portion;
placing a dielectric element on one of either the first voltage plane or the second voltage plane;
superimposing the first and second leadframes such the first voltage leads are interspersed with the second voltage leads, such that the second voltage plane overlies the dielectric element and the first voltage plane to form a decoupling capacitor, and such that inner lead portions of the first voltage leads and inner lead portions of the second voltage leads lie substantially in a common plane;
electrically coupling the inner lead portions of the first voltage leads to the first voltage bond pads of the semiconductor die;
and
electrically coupling the inner lead portions of the second voltage leads to the second voltage bond pads of the semiconductor die.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor device with integral decoupling capacitor

Life of this patent

Semiconductor device with integral decoupling capacitor

Life of this patent

Abstract

Claims17