US 5,212,109 AGranted

Method for forming PN junction isolation regions by forming buried regions of doped polycrystalline or amorphous semiconductor

AssigneeNissan Motor Co., Ltd.

InventorTeruyoshi Mihara

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Abstract

In a semiconductor device having island regions formed in a surface area of a substrate, the island regions are electrically isolated from the substrate via buried regions formed of polycrystalline or amorphous semiconductor, without use of epitaxial growth technique. Since the polycrystalline or amorphous semiconductor includes a great number of recombination centers, parasitic operation between the elements formed on the semiconductor substrate can be prevented. Further, the buries regions are excellent in heat conductivity, the breakdown resistance against surge voltages or static electricity can be improved. Furthermore, when applied to a CMOS, it is possible to prevent latch up action caused by a parasitic thyristor formed in the CMOS, by the presence of the buried regions including a great number of recombination centers.

Claims8

Dependent claims

A method of producing a semiconductor device having at least two island regions formed in a surface area of a substrate, comprising the steps of:

(a) preparing a first conductivity type semiconductor substrate;
(b) forming a second conductivity type region by diffusion in the surface area of the substrate, to provide a second conductivity type island region later;
(c) forming an insulating film on the surface area of the substrate for masking of the surface area of the substrate, to provide first and second conductivity type island regions under the formed insulating film later;
(d) forming vertical grooves in the surface area of the substrate by etching on the basis of the formed insulating masking film, to form the island regions between the two adjacent vertical grooves;
(e) forming enlarged grooves and the first and second conductivity type island regions by etching side walls of the formed vertical grooves;
(f) filling up the enlarged grooves with a second conductivity type doped polycrystalline or amorphous semiconductor to obtain a buried region for enclosing the island regions so that the island regions are isolated from the substrate;
(g) partially forming an oxide film on only the surface area of the buried region by oxidization to obtain a substrate board;
and
(h) forming semiconductor elements in the formed island regions to produce a semiconductor device.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/762,264Filed 20 Sep 1991 · continuation
Priority: JP 1-12864124 May 1989
Granted: 18 May 1993
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10P 90/1906
Preparing vertically inhomogeneous wafers: preparing SOI wafers
H10W 10/061
Manufacture or treatment: using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
H10W 10/181
Isolation regions comprising dielectric materials: semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers