US 5,212,106 AGranted

Optimizing doping control in short channel MOS

AssigneeAdvanced Micro Devices, Inc.

InventorsDarrell M. Erb, Zoran Krivokapic

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Abstract

An improved process is provided for fabricating short channel complementary metal oxide semiconductor devices. The devices comprise source and drain regions separated by gate regions. The process comprises forming a shallow channel doping region (12') beneath the surface of a semiconductor (10) and forming source-drain regions (20') of opposite conductivity type (formerly known as lightly doped drain structures) on either side of the shallow doping region. A gate oxide (16) is formed on the surface of the semiconductor above the shallow channel doping region and a gate electrode (18) is formed to the gate oxide prior to the formation of the shallow channel doping region. The process permits spacing of the channel doping from the source-drain doping with self-alignment. Further, the doping of the source-drain regions is not constrained to the values of the lightly-doped structures of the prior art.

An improved process for fabricating short channel metal oxide semiconductor devices comprising source and drain regions separated by gate regions, wherein the process of forming a shallow channel doping region includes forming said shallow channel doping region beneath the surface of a semiconductor, forming source-drain regions of opposite conductivity type on either side of said shallow doping region, forming a gate insulator on the surface of said semiconductor above said shallow channel doping region and extending over a portion of said source-drain region adjacent said shallow channel doping region, and forming a gate electrode to said gate oxide, the improved process including:

(a) forming a doped glass layer on said substrate, said doped glass layer acting as a source of dopant to form said source-drain regions of opposite conductivity by subsequent diffusion into said silicon substrate at an elevated temperature;
(b) forming an insulating layer and said doped glass layer;
(c) patterning said insulating layer and said doped glass layer to form vertical structures which define said gate region, said vertical structures disposed on either side of said gate region;
(d) forming an oxide film on the exposed surface of said vertical structures;
(e) anisotropically etching said oxide film to leave said oxide film on the sidewalls of said vertical structures to thereby form oxide spacers;
(f) forming said gate insulator in said gate region;
(g) forming a polysilicon coating on said gate insulator and on said vertical structures to provide a narrowed spacing between said vertical structures, said narrowed spacing being less than the distance separating said source and drain regions;
and
(h) implanting ions through said polysilicon coating and said gate insulator into said gate region to form said shallow channel doping region to thereby laterally space said shallow channel doping region by a distance S from said sidewalls of said vertical structures and to self-align said shallow channel doping region to said source-drain regions, said shallow channel doping region centered between said source-drain regions and separated therefrom.

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Facts

Application

07/881,002Filed 7 May 1992

Granted

18 May 1993

Term ends

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Classification8 codes

H10D 30/0273
Of lateral single-gate IGFETs: forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Abstract

Claims14