Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline

A microprocessor comprising;

• an instruction fetch unit which fetches instructions of first instruction set from storage external to the microprocessor;
• an instruction decoding unit which decodes instructions fetched by said instruction fetch unit and outputs decoded results;
• an operation unit which performs operations on one or more data items in accordance with the instructions of said first instruction set and instructions of a second instruction set different from said first instruction set;
• a plurality of registers which are operated by the instructions of said first instruction set;
• a control unit, under a first mode, which receives
• the decoded result or results of instructions of said first instruction set from a first path passing through said instruction fetch unit and said instruction decoding unit, and then performs pipeline processing by coordinating the operation of said instruction fetch unit, said instruction decoding unit and said operation unit in accordance with
• the received instructions of said first instruction set, and
• under a second mode, which receives instructions of said second instruction set from a second path passing through neither said instruction fetch unit nor said instruction decoding unit, and then diagnoses at least one of said instruction fetch unit, said instruction decoding unit and said operation unit in accordance with the received instructions of said second instruction set, and
• means, when a predetermined signal is inputted under said first mode, for transferring operation mode from said first mode to said second mode while holding the values of said registers intact at inputting of said predetermined signal.

A microprocessor comprising:

• an instruction fetch unit which fetches instructions of first instruction set from storage external to the microprocessor;
• an instruction decoding unit which decodes instructions fetched by said instruction fetch unit and outputs decoded results;
• an operation unit which performs operation on data items in accordance with the instructions of said first instruction set and instructions of a second instruction set different from said first instruction set;
• a plurality of registers which are operated by the instructions of said second instruction set;
• a control unit, under a first mode, which receives
• the decoded result or results of instructions of said first instruction set from a first path passing through said instruction fetch unit and said instruction decoding unit, and then executes pipeline processing by operating said instruction fetch unit, said instruction decoding unit and said operation unit in parallel and in mutual association with each other in accordance with the received instructions of said first instruction set, and
• under a second mode, which receives instructions of said second instruction set from a second path passing through neither said instruction fetch unit nor said instruction decoding unit, and then diagnoses at least one of said instruction fetch unit, said instruction decoding unit and said operation unit in accordance with the received instructions of said second instruction set, and
• means, when a predetermined instruction of said second instruction set is executed under said second mode, for transferring operation mode from said second mode to said first mode while holding the values of said registers intact at executing of said predetermined instruction.

A microprocessor comprising:

• an instruction fetch unit which fetches instructions of first instruction set from storage exterior to the microprocessor;
• an instruction decoding unit which decodes instructions fetched by said instruction fetch unit and outputs decoded results;
• an operation unit which executes performs operations on data items in accordance with the instructions of said first instruction set and instructions of a second instruction set different from said first instruction set;
• a plurality of registers which are operated by the instructions of said first instruction set and said second instruction set;
• a control unit, under a first mode, which receives
• the decoded result or results of instructions of said first instruction set from a first path passing through said instruction fetch unit and said instruction decoding unit, and then executes pipeline processing by operating said instruction fetch unit, said instruction decoding unit and said operation unit in parallel and in mutual association with each other in accordance with the received instructions of said first instruction set, and
• under a second mode, which receives instructions of said second instruction set from a second path passing through neither said instruction fetch unit nor said instruction decoding unit, and then diagnoses at least one of said instruction fetch unit, said instruction decoding unit and said operation unit in accordance with the received instructions of said second instruction set, and
• means, when a predetermined signal is inputted under
• said first mode, for transferring operation mode from said first mode to said second mode while holding the values of said registers intact at inputting of said predetermined signal, and
• when a predetermined instruction of said second instruction set is executed under said second mode, for transferring operation mode from said second mode to said first mode while holding the values of said registers intact at executing of said predetermined instruction.