Multi-processor system for detecting a malfunction of a dual port memory
AssigneeMinolta Camera Kabushiki Kaisha
InventorHiroshi Tomita
Life of this patent
Estimating the term…
Abstract
A multi-processor system wherein two processors are connected through a dual port memory which receives from one of the processors an interruption request signal together with the data to be transmitted to the other processor. The dual port memory then generates an interrupt signal for the other processor so that the other processor can fetch the data from the dual port memory using an interrupt procedure. The one processor also receives the interrupt signal transmitted by the dual port memory in order to confirm the status of the interrupt signal generating function of the dual port memory.
Claims15
A multi-processor system, comprising:
- two processors;
- a dual port memory means for receiving from one of the processors an interrupt request signal together with data to be transmitted to the other processor and for transmitting an interrupt signal to said other processor;
- said other processor having means for fetching said data from said dual port memory means during an interrupt procedure responsive to said interrupt signal;
- and
- means, in said one processor and responsive to said interrupt signal transmitted from the dual port memory means to said other processor in response to said interrupt request signal generated from said one processor, for confirming the status of the interrupt signal generating function of said dual port memory means.
A multi-processor system having two processors, a dual port memory means for receiving from one of the processors an interrupt request signal together with data to be transmitted to the other processor and for transmitting an interrupt signal to said other processor, said other processor having means for fetching said data from said dual port memory means during an interrupt procedure responsive to said interrupt signal, said multi-processor system comprising:
- a first means for returning said interrupt signal transmitted by said dual port memory means to said other processor to said one processor;
- and
- a second means for returning said interrupt signal transmitted by said dual port memory means to said one processor to said other processor;
- wherein both said one and said other processor can confirm the status of the interrupt signal generating function of the dual port memory means.
A multi-processor system, comprising:
- first and second processors each having a data input/output terminal for receiving and transmitting data, an output terminal for transmitting an interrupt request signal and an input terminal for receiving an interrupt signal, each processor performing an interrupt procedure based on said signals;
- a memory having data input/output terminals for receiving and transmitting data, input terminals for receiving said interrupt request signals and output terminals for outputting said interrupt signals, said memory outputting said interrupt signal together with said data to be transmitted to one of said processors when said interrupt request signal is received from the other of said processors;
- first circuit means for returning said interrupt signal transmitted from said memory to said second processor to said first processor;
- and
- second circuit means for returning said interrupt signal transmitted from said memory to said first processor to said second processor.
A multi-processor system comprising:
- a first processor;
- a second processor;
- a dual port memory means for receiving from said first processor an interrupt request signal and for transmitting an interrupt signal to said second processor;
- and
- an interrupt transmission means for transmitting another interrupt signal from said first processor to said second processor without interaction with said dual port memory means.
Dependencies are inferred from the claim text.