Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor

A clocking control circuit for a computer system, said computer system having a microprocessor, a cache controller operatively connected to said microprocessor for controlling cache memory, and support interface circuitry operatively connected to said cache controller, said clocking circuit comprising:

• means for increasing the time duration of signals transmitted to said support interface circuitry from said cache controller wherein said means for increasing the time duration is coupled to said cache controller and to said support interface circuitry;
• means for decreasing the time duration of signals transmitted to said cache controller from said support interface circuitry;
• and
• means for receiving a clock signal which drives said microprocessor and said cache controller and for supplying to said support interface circuitry a support clock signal having a frequency lower than that of said clock signal.