US 5,210,854 AGranted

System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version

AssigneeDigital Equipment Corporation

InventorsArthur J. Beaverton, Thomas E. Hunt

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Abstract

Firmware resident in electrically erasable programmable read only memory ("EEPROM") can be updated by a user while maintaining the intelligence of a computer system during the updating process by a control logic device. The control logic device decodes address and control signals to provide a hardware partitioning of the firmware resident in the EEPROMs to prevent writing to protected partitions of the firmware. Transfer vectors are used to provide indirect accessing of subroutines resident in the firmware. During an updating process, a new version of a subroutine is stored in a free area in the EEPROMs before the transfer vector pointing to the old version of the subroutine is updated. The window of vulnerability to errors during the updating process is minimized by only updating a page of memory containing the transfer vector that points to the old version of the subroutine after the new version has been stored.

Claims7

Dependent claims

A digital computer memory system comprising:

an electrically erasable programmable read-only memory containing firmware, having a plurality of address and data inputs and a plurality of locations, each location having an address, and a control input which permits writing to the electrically erasable programmable read-only memory, the electrically erasable programmable read-only memory is partitioned into a protected area and an unprotected area, the unprotected area having a conditionally writable area;
a central processing unit having a plurality of data outputs, a plurality of address outputs, a control output and an update enable output;
an address bus coupling the plurality of address inputs in the electrically erasable programmable read-only memory to the plurality of address outputs of the central processing unit;
a data bus coupling the plurality of data inputs in the electrically erasable programmable read-only memory to the plurality of data outputs of the central processing unit;
and
a control logic device having a plurality of address inputs, a control input, an update enable input and an output, the plurality of address inputs coupled to at least a portion of the address bus, the output coupled to the control input of the electrically erasable programmable read-only memory, the control input coupled to the control output of the central processing unit, and the update enable input coupled to the update enable output of the central processing unit;
the control logic device responsive to the control output of the central processing unit and an address transmitted on the at least a portion of the address bus, generating a write enable signal when the address is within the unprotected area of the electrically erasable programmable read-only memory and inhibiting the write enable signal when the address is within the protected area of the electrically erasable programmable read-only memory;
the control logic device generating in response to the control input, the update enable input and the address transmitted on the at least a portion of the address bus, a write enable signal when the address is within the conditionally writable area of the electrically erasable programmable read-only memory and inhibiting the write enable signal when the address is within the protected area of the electrically erasable programmable read-only memory.

5 more elements

A method of updating a computer program stored in an electrically erasable programmable read-only memory having a plurality of inputs and a plurality of locations, each location having an address, the electrically erasable programmable read-only memory is partitioned into an unprotected partition and a protected partition, comprising the steps of:

(a) coupling a central processing unit to the electrically erasable programmable read-only memory via an address bus and a data bus;
(b) providing a first transfer vector in the protected partition of the electrically erasable programmable read-only memory;
(c) providing a second transfer vector in the unprotected partition of the electrically erasable programmable read-only memory, the second transfer vector contains an address of a location of the beginning of the computer program, the first transfer vector contains an address of a location in the electrically erasable programmable read-only memory where the second transfer vector is stored;
(d) initiating an update of the computer program stored in the electrically erasable programmable read-only memory by storing a new version of the computer program in memory locations in the electrically erasable programmable read-only memory that do not contain the old version of the computer program, such that if an error occurs while updating, the old version of the computer program stored in the electrically erasable programmable read-only memory is not affected and the central processing unit can still access the old version of the computer program stored in the electrically erasable programmable read-only memory;
and
(e) after the new version of the computer program is stored in the electrically erasable programmable read-only memory, updating the second transfer vector to contain the starting address where the new version of the computer program is stored in the electrically erasable programmable read-only memory, such that the amount of time required to update the second transfer vector is constant and independent of the amount of time required to store the new version of the computer program in the electrically erasable programmable read-only memory thereby minimizing a window of vulnerability to errors during firmware updates.

3 more elements

Dependencies are inferred from the claim text.