Memory address space determination using programmable limit registers with single-ended comparators

An apparatus for determining if a memory address value developed in a computer system is within any of a plurality of memory address regions, the computer system having a given address space, the address space being divided into regions based on the beginning of the address space and a memory address value intermediate in the address space, the apparatus comprising:

• means for performing an address decode of said developed memory address value to determine if said developed memory address value is greater than the intermediate memory address value and for producing an intermediate address decode signal indicative thereof;
• a first storing means for storing a first memory address value associated with a first memory address region at the beginning of the address space;
• a second storing means for storing a second memory address value associated with a second memory address region having one boundary at the intermediate memory address value;
• a third storing means for storing a third memory address value associated with a third memory address region having one boundary at the intermediate memory address value;
• a first comparing means for comparing the developed memory address with said first memory address value stored in said first storing means and determining if said developed memory address value is less than said stored first memory address value, said first comparing means generating a signal indicating whether the developed memory address value resides in said first address region based only on said comparison of the developed memory address value with said first memory address value stored in said first storing means;
• a second comparing means for receiving said intermediate address decode signal and for comparing the developed memory address value with said second memory address value stored in said second storing means and for determining if said developed memory value is greater than said stored second memory address value and producing a second signal indicative thereof and for defeating operation of said determining if said intermediate address decode signal indicates that said developed memory address value is greater than said second memory address value, said second indicating signal indicating whether the developed memory address value resides in said second address region based only on said comparison of the developed memory address value with said second memory address value stored in said second storing means and said intermediate address decode signal;
• and
• a third comparing means for receiving said intermediate address decode signal and for comparing the developed memory address value with said third memory address value stored in said third storing means and for determining if said developed memory address value is less than said stored third memory address value and producing a signal indicative thereof and for defeating operation of said determining if said intermediate address decode signal indicates that said developed memory address value is not greater than the intermediate address value, said third indicating signal indicating whether the developed memory address value resides in said third address region based only on said comparison of the developed memory address value with said third memory address value stored in said third storing means and said intermediate address decode signal.