Pseudo set-associative memory caching arrangement

A pseudo set-associative memory cacheing arrangement for use in conjunction with a processor interfacing to a main memory and adapted to support a cache memory, the arrangement comprising a plurality of cache memory banks each comprising a respective number of addressable locations defined by cache addresses comprising n least significant bits of a main memory address and each being responsive to a cache address, a read signal from the processor and a cache select signal for outputting the data at the addressed location to the data bus of the processor, a plurality of cache select circuits each one associated with a respective one of the cache memory banks and each one being responsive to m most significant bits of a main memory address and predetermined control signals for asserting a cache bank select signal to its associated cache memory bank when said m most significant bits correspond to an address within a predetermined respective main memory range of contiguous addresses.

A method of cacheing instruction data in a data processing system including a processor interfacing to a main memory and adapted to support a cache memory comprising a plurality of cache memory banks each comprising a plurality of addressable locations defined by cache addresses comprising n least significant bits of a main memory address, the method comprising the step of allocating a respective range of contiguous main memory addresses to each of the cache memory banks thereby mapping each memory bank to a respective portion of main memory.