Data processor having instruction varied set associative cache boundary accessing

A data processor having instruction varied set associative cache boundary accessing, comprising:

• instruction processing and decoding means for receiving a plurality of successive instructions and decoding the successive instructions, the instruction decoding means providing a set associative cache boundary control signal for a subsequent set associative cache access;
• set associative cache control means having an input coupled to the instruction processing and decoding means for receiving the set associative cache boundary control signal and providing an encoded enable signal;
• a set associative cache coupled to set associative cache control means for receiving the encoded enable signal and having a predetermined number of lines of information of predetermined bit length, said set associative cache using the encoded enable signal to dynamically select one of a plurality of predetermined lengths of a line of information to be accessed in the set associative cache and provided by the set associative cache, the set associative cache normally providing only one-half line of information in response to the encoded enable signal in order to conserve power in the data processor and providing a full line of information only in response to the data processor requiring the complete line of information;
• a holding register having an input coupled to the set associative cache and having an output, the holding register storing information from the set associative cache;
• and
• a multiplecor having an input coupled to the output of the holding register, and having an output coupled to the instruction processing and decoding means for providing a selected portion of information provided by the set associative cache.