External memory accessing system

In a processor of the type which processes instructions in serial stages including a fetch stage, a decode stage, an execute stage, and a write-back stage, and which includes an external memory for storing data to be executed upon, said external memory including a plurality of storage locations with each said location having a unique physical storage address, and wherein said processor further includes a first plurality of registers, each said first plurality of registers having a unique address and being arranged for storing an untranslated address corresponding to one of said external memory locations, and a second plurality of registers, each said second plurality of registers having a unique address and being arranged for storing data to be executed upon by said processor, and wherein the addresses stored in said first plurality of registers require translation to said physical external memory location addresses to permit said external memory locations to be accessed, a new and improved system for efficiently accessing the data stored in one of said external memory locations and providing said data to one of said second plurality of registers responsive to a currently fetched load instruction including the address of one of said first plurality of registers, said system comprising:

• a physical address cache for storing a plurality of entries including the addresses of said first plurality of registers and the corresponding translated external memory address locations for those ones of said first plurality registers which were used for the execution of previous load instructions;
• means responsive to said currently fetched load instruction for determining, during said decode stage of said load instruction, if the address of said one of said first plurality of registers contained in said currently fetched load instruction is stored in said physical address cache;
• and
• means for conveying to said external memory at the beginning of said execution stage of said load instruction, the previously translated physical address of said memory location corresponding to said address of said one of said first plurality of registers if said address of said one of said first plurality of registers is contained in said physical address cache.