Address space control apparatus for virtual memory systems

An address space control apparatus in a virtual memory system having a storage means and a plurality of general-purpose register means usable as registers which supply data for address calculation, wherein address information specified by an instruction is used to calculate a logical address in an address space, said logical address being combined with an address space identifier defining the address space for translation into a real address in said storage means, said address space control apparatus comprising:

• a first component information register means for containing first component information for determining an address space, said first component information including a plurality of address space identifiers contained in a plurality of entries within said first component information register means:
• a means for reading, in response to designation of a first general-purpose register means as a base register by an instruction, second component information, out of a second general-purpose register means corresponding to said first general-purpose register means, for determining an address space;
• and
• a means for determining, by use of said first and second component information, an address space identifier to be combined with a logical address, including an entry designator register means for containing an entry designator designating one of said plurality of entries, and an adder means for producing an entry selection signal by adding said entry designator and said second component information.

An address space control apparatus in a virtual memory system having a storage means and a plurality of general-purpose register means usable as registers which supply data for address calculation, wherein address information specified by an instruction is used to calculate a logical address in an address space, said logical address being combined with an address space identifier defining the address space for translation into a read address in said storage means, said address space control apparatus comprising:

• an identifier register means for containing an address space identifier;
• an address adder means which receives as one of its inputs a double-length base address formed by coupling the contents of said identifier register means with the contents of a first general-purpose register means designated as a base register by an instruction, the contents of said identifier register means occupying the high-order part of said double-length base address, and receives as another one of its inputs the contents of a double-length index register means formed by coupling a second general-purpose register means designated as an index register by said instruction with a third general-purpose register means corresponding to said second general-purpose register means;
• a means for outputting the low-order half of the output of said address adder means as a logical address;
• and
• a means for outputting the high-order half of the output of said address adder means as an address space identifier to be combined with said logical address.

An address space control apparatus in a virtual memory system having a storage means and a plurality of general-purpose register means usable as registers which supply data for address calculation, wherein address information specified by an instruction is used to calculate a logical address in an address space, said logical address being combined with an address space identifier defining the address space for translation into a real address in said storage means, said address space control apparatus comprising:

• an identifier register means for containing an address space identifier;
• a shifter means for shifting towards a higher-order position by a specified length the contents of a general-purpose register means designated by an instruction;
• an address adder means receiving as a first input the output of said shifter means;
• and
• a shift-length register means for storing information which specifies a length of the shift to be performed by said shifter means.