Method and apparatus for providing a memory address from a computer instruction using a mask register

In a computer system which performs a quality of plurality of instructions when executing a program, said program utilizing a memory having a maximum memory address size of a first word size, and memory addressing circuitry for accessing said memory, said computer system comprising a plurality of multi-bit registers, each multi-bit register having a second word size greater than said first word size, said plurality of instructions comprising a first instruction that designates a first set of at least two registers of said plurality of multi-bit registers to be added to form an access address for accessing memory, said access address being a sum of contents of a first subset of bits of said first set of at least two registers, a method for providing said access address comprising the steps of:

• providing a set of valid bits, said set of valid bits equal in number to the size of said first word size if said first instruction is being performed;
• summing contents of a set of registers to generate a summed address;
• performing a logical AND operation with the valid bits and the summed address to generate the access address;
• coupling said access address directly to said memory addressing circuitry to responsively access said memory at said access address;
• wherein said first instruction having a word size less than the word size of the computer system can be executed without being affected by data present in bits of said plurality of multi-bit registers which are not valid bits.

In a computer system including means for outputting an access address of a first word size of (L) bits in conjunction with a first program designed for use in conjunction with said first word size of (L) bits, said means for outputting an access address of a first word size of (L) bits comprising a first register the size of said first word size of (L) bits, a second register the size of said first word size of (L) bits, an adder coupled to said first register and said second register, a holding register the size of said first word size of (L) bits coupled to said adder, a plurality of logic gates coupled to said holding register, and a mask register of said first word size of (L) bits coupled to said plurality of logic gates, wherein said access address is output directly from said plurality of logic gates, a method for outputting an access address of a second word size of (S) bits for a program designed for use in conjunction with said second word size of (S) bits, wherein said second word size of (S) bits is less than said first word size of (L) bits, said method comprising the steps of:

• setting (S) bits in said mask register of said first word size of (L) bits equal to a first logic state;
• setting (L-S) bits in said mask register of said first word size of (L) bits equal to a second logic state;
• coupling a first plurality of bits in said first register of said first word size of (L) bits and a second plurality of bits in said second register of said first word size of (L) bits to said adder;
• said adder adding said first plurality of bits and said second plurality of bits and coupling a result of said adding to said holding register of said first word size of (L) bits;
• said holding register of said first word size of (L) bits coupling said result of said adding to said plurality of logic gates;
• said mask register of said first word size of (L) bits coupling said (S) bits and said (L-S) bits set in said mask register to said plurality of logic gates;
• said plurality of logic gates, responsive to said coupling of said result of said adding, said (S) bits, and said (L-S) bits to said plurality of logic gates, outputting an access address of said second word size of (S) bits.