US 5,210,838 AGranted

Method and apparatus for predicting the effective addresses of future memory load operations in a microprocessor

AssigneeSun Microsystems, Inc.

InventorEric H. Jensen

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Abstract

A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.

Claims6

Dependent claims

A method for loading a data value from a memory into a microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction and having a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address, said method comprising the steps of:

a) updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating step comprising the substeps of:
i) indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction,
ii) moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and
iii) storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line;
b) loading a data value from said memory for a future LOAD instruction, said loading step comprising the substeps of:
i) indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter,
ii) predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and
iii) loading said data value from said memory using said predicted effective address;
and
c) using said data value if the predicted effective address matches an effective address of the future LOAD instruction.

7 more elements

An apparatus in a microprocessor for loading a data value from a memory into the microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction, said apparatus comprising:

a) a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address;
b) means for updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating means comprising:
i) means for indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction,
ii) means for moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and
iii) means for storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line;
c) means for loading a data value from said memory for a future LOAD instruction, said loading means comprising:
i) means for indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter,
ii) means for predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and
iii) means for loading said data value from said memory using said predicted effective address;
and
d) means for using said data value if the predicted effective address matches an effective address of the future LOAD instruction.

8 more elements

Dependencies are inferred from the claim text.