US 5,210,836 AGranted

Instruction generator architecture for a video signal processor controller

AssigneeTexas Instruments Incorporated

InventorsJim Childers, Peter Reinecke, Moo-Taek Chung, Hiroshi Miyaguchi

Life of this patent

Estimating the term…

Loading patent…

Abstract

A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

Claims9

Dependent claims

An instruction generator circuit having inputs for receiving operating mode signals from an external source and an output for supplying instructions to a video signal processing device having a plurality of one-bit parallel operating processor elements, each processor element having inputs for receiving the instructions and executing instruction in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, the instruction generator circuit comprising:

an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input;
a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal;
a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device;
a register output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device;
an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction.

2 more elements

A television receiving system for receiving a standard television transmission signal and producing a picture comprising:

an analog to digital converter for converting the received standard television transmission signal into digital picture samples;
a processor system having an input connected to said analog to digital converter for receiving said digital picture samples, an output for generating processed digital picture samples, said processor system including
a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving digital picture samples, instruction inputs for receiving the instructions and data outputs for generating digital picture samples, each processor element executing instructions converting digital picture samples into processed digital picture samples in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction,
an instruction generator circuit including
an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input,
a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal,
a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device,
a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device,
an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction;
a digital to analog converter connected to said processor system for converting said processed digital picture samples into an analog picture signal;
a display unit connected to said digital to analog converter for generating a visual display corresponding to said analog picture signal.

8 more elements

A video system comprising:

a video signal receiver for generating a picture signal:
a controller capable of generating mode signals;
and
a processor system having an input connected to said video signal receiver for receiving said picture signal, an output for generating a processed picture signal, said processor system including
a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving picture signals, instruction inputs for receiving the instructions and data outputs for generating processed picture signals, each processor element executing instructions converting picture signals into processed picture signals in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction,
an instruction generator circuit including
an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input,
a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal,
a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device,
a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device,
an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction;
and
a video display connected to said processor system for forming a visual display corresponding to said processed picture signal.

10 more elements

Dependencies are inferred from the claim text.