High speed transfer of instructions from a master to a slave processor

A method for operating a computer system to transfer a plurality of instructions from a scalar processor coupled to a vector processor, the instructions each having an opcode and a set of operands, the method comprising the steps of:

• a) sending the opcode for each of the instructions to be executed from the scalar processor to the vector processor, the step of sending the opcode further comprising the step of operating a first micro-engine in the scalar processor to send a new instruction signal and the opcode to a vector opcode decoder and determining by the vector opcode decoder whether the opcode is for a vector instruction, the vector opcode decoder then issuing a new vector instruction signal to the vector processor when the opcode is for a vector instruction, the new vector instruction signal instructing the vector processor to read the opcode from the scalar processor;
• b) storing the opcode in a first buffer in the vector processor;
• c) operating the scalar processor to fetch, from a source of operands, process, and validate the set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor;
• d) delivering a signal from the scalar processor to the vector processor indicating the scalar processor is ready to deliver a processed set of operands for an instruction;
• e) delivering the processed set of operands associated with the opcode sent to the first buffer to a second buffer in the vector processor;
• f) moving the opcode, associated with the processed set of operands, from the first buffer to the second buffer upon receiving a first operand in the processed set of operands from the scalar processor;
• and
• g) invalidating any opcodes in the first buffer having an associated set of operands which, when fetched and processed by the scalar processor, are determined to be invalid.

A method for operating a computer system to transfer a plurality of instructions from a scalar processor to a vector processor, with the scalar processor being coupled to the vector processor, the instructions each having an opcode and a set of operands, the method comprising the steps of:

• a) sending the opcode for each of the instructions to be executed from the scalar processor to the vector processor and storing the opcodes in a first buffer in the vector processor wherein the step of sending the opcode further comprises the step of:
• operating a first micro-engine in the scalar processor to send a new instruction signal and the opcode to a vector opcode decoder and determining by the vector opcode decoder whether the opcode is for a vector instruction, said vector opcode decoder then issuing a new vector instruction signal to the vector processor when the opcode is for a vector instruction, the new vector instruction signal instructing the vector processor to read the opcode from the scalar processor;
• b) operating the scalar processor to sequentially fetch, from a source of operands, and process the set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor;
• c) pre-decoding the opcodes in the first buffer in the vector processor while awaiting a delivery of the associated processed set of operands from the scalar processor;
• d) determining the validity of each of the set of operands;
• e) delivering each valid processed set of operands to the vector processor;
• f) discarding each opcode in the first buffer whose associated set of operands is not valid;
• g) forming each of the plurality of instructions from each opcode in the first buffer and its associated set of operands;
• and
• h) executing each of the plurality of instructions.

A method for operating a computer system to transfer a plurality of instructions from a master processor coupled to a slave processor, said instructions each having an opcode and a set of operands, the method comprising the steps of:

• a) sending the opcode for each of the instructions to be executed from the master processor to the slave processor and storing the opcode in a first buffer in the slave processor;
• b) operating the master processor to fetch, from a source of operands, and to process a set of operands for each opcode sent to the first buffer for each of the instructions to be executed by the slave processor;
• c) determining whether an exception has occurred during the fetching and processing of the set of operands associated with each opcode sent to the first buffer;
• d) delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction;
• e) delivering the processed set of operands for each opcode sent to the first buffer, to a second buffer in the slave processor;
• f) moving the opcode, associated with the processed set of operands, from the first buffer to the second buffer upon receiving the processed set of operands from the master processor;
• and
• g) invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, said instructions each having an opcode and a set of operands, the interface comprising:

• a) a first micro-engine in the master processor for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means for storing each opcode in a first buffer in the slave processor, the first buffer comprising a two opcode deep buffer;
• b) a second micro-engine in the master processor for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor;
• c) means for pre-decoding the opcodes in the first buffer by the slave processor while awaiting delivery of the processed sets of operands from the master processor;
• d) a third micro-engine in the master processor for determining the validity of each set of operands, for delivering a first signal from the master processor to the slave processor indicating the master processor is ready to deliver a valid processed set of operands, for delivering a second signal from the master processor to the slave processor directing the slave processor to discard each opcode whose associated set of operands is not valid;
• and
• e) means for delivering the valid processed set of operands to the slave processor, discarding each opcode in the first buffer which is not valid, and executing each of the instructions.

A scalar-vector processor interface for transferring a plurality of instructions from a scalar processor coupled to a vector processor, the instructions each having an opcode and a set of operands, the interface comprising:

• a) a first micro-engine, in the scalar processor, for sending the opcode for each of the instructions to be executed from the scalar processor to the vector processor and means, in the vector processor, for storing each opcode in a first buffer in the vector processor;
• b) a second micro-engine, in the scalar processor, for operating the scalar processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor;
• c) a third micro-engine, in the scalar processor, for determining the validity of a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor, and, for delivering a signal from the scalar processor to the vector processor indicating the scalar processor is ready to deliver a valid processed set of operands for an instruction;
• d) means, in the scalar processor, for delivering the valid processed set of operands associated with each opcode sent to the first buffer to a second buffer in the vector processor;
• e) means, in the vector processor, for moving the opcode, associated with the valid processed set of operands, from the first buffer to the second buffer upon receiving a first operand in the valid processed set of operands from the scalar processor;
• and
• f) means for invalidating any opcodes in the first buffer having an associated set of operands which, when fetched and processed by the scalar processor, are determined to be invalid.

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, the instructions each having an opcode and a set of operands, the interface comprising:

• a) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor;
• b) means, in the master processor, for operating the master processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor;
• c) means, in the master processor, for determining whether an exception has occurred during the fetching and processing of each of the set of operands associated with each opcode stored in the first buffer;
• d) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction;
• e) means, in the master processor, for delivering the processed set of operands associated with each opcode sent to the first buffer to a second buffer, in the slave processor;
• f) means, in the slave processor, for moving the opcode, associated with the processed set of operands, from the first buffer to the second buffer upon receiving the processed set of operands from the master processor;
• and
• g) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

A computer system, comprising:

• a) a master processor for transferring a plurality of instructions, the instructions each having an opcode and a set of operands;
• b) a slave processor, coupled to the master processor, for receiving and executing the plurality of instructions;
• c) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor;
• d) means, in the master processor, for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor;
• e) means, coupled to the first buffer, for pre-decoding the opcodes in the first buffer by the slave processor while awaiting a delivery of the processed set of operands from the master processor;
• f) means, in the master processor, for determining whether an exception occurred during the fetching and processing of the set of operands;
• g) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction;
• h) means, in the master processor, for delivering a processed set of operands to a second buffer in the slave processor;
• i) means, in the slave processor, for moving the opcode associated with each processed set of operands from the first buffer to the second buffer upon receiving the processed sets of operands from the master processor;
• and
• j) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.