US 5,210,828 AGranted

Multiprocessing system with interprocessor communications facility

AssigneeInternational Business Machines Corporation

InventorsTimothy V. Bolan, Josephine A. Boston, George A. Fax, Donald J. Hanrahan, Bernhard Laubli, David A. Ring, Alfred T. Rundle, David J. Shippy

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Abstract

A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.

A communication system comprising:

a first processor;
a second processor;
a first holding register dedicated and independently coupled to said first processor to receive from said first processor interrupt commands, write messages and read requests;
a second holding register dedicated and independently coupled to said second processor to receive from said second processor interrupt commands, write messages and read requests, each of the holding registers receiving the respective interrupt commands, messages and requests independently of the interrupt commands, messages and requests received by the other holding register;
a first interrupt storage register coupled and dedicated to said first processor to supply interrupts thereto, said interrupts being sent by said second processor to notify said first processor of a message sent by said second processor;
a second interrupt storage register coupled and dedicated to said second processor to supply interrupts thereto, said interrupts being sent by said first processor to notify said second processor of a message sent by said first processor;
mailbox means for storing a multiplicity of messages sent by said first and second processors, said messages being transmitted to said second and first processors, respectively, upon request by said second and first processors;
decode means, coupled to said mailbox means and said first and second interrupt storage registers, for routing interrupt commands stored in said first and second holding registers to said second and first interrupt storage registers, respectively, routing messages from said first and second processors to said mailbox means, and processing read requests by directing said mailbox means to output the requested message to the requesting processor;
and
means, coupled between said holding registers and said decode means, for arbitrating access to said decode means between interrupt commands, messages, and requests stored in said first and second holding registers.

7 more elements

Abstract

Claims4