Process for the intermediate amplification of digital signals and intermediate amplifiers for digital signals
AssigneeRichard Hirschmann GmbH & Co.
InventorsBernhard Schmid, Rainer Schenkyr
Life of this patent
Estimating the term…
Abstract
An intermediate amplification process for digital signals with pulse regeneration, determines the phase difference between the receiving timing signal and the local transmission timing signal and alters the phase of the local transmission timing signal as a function of the phase difference. It is particularly advantageous that the receiving timing signal is used as the transmission timing signal as soon as the phase difference becomes essentially zero. It is possible in this manner to minimize both the startup time delay and the packet spacing, as the number of bits to be stored intermediately may be kept low.
Claims28
A process for intermediate amplification of digital signals transmitted as data packets, with amplitude and pulse regeneration, wherein pulse regeneration comprises the steps of:
- derivation of a receiving timing signal from a signal received;
- reading in bits of the signal received with the receiving timing signal into a buffer memory;
- and
- reading out the bits from buffer memory in accordance with a local transmission timing signal, altering the phase of said local transmission timing signal as a function of a phase difference between said receiving timing signal and said local transmission timing signal;
- recognizing an incoming data packet;
- transmitting a synthetic preamble essentially immediately following recognition of an incoming data packet and prior to completion of said step of derivation of a receiving timing signal.
A digital signal repeater comprising:
- an amplitude and pulse regeneration circuit for data packets, wherein said regeneration circuit includes a receiving timing signal deriver,
- a buffer memory connected to said receiving timing signal deriver,
- a control circuit connected to said buffer memory and said receiving timing signal deriver,
- a local transmission timing signal generator,
- a phase comparator connected to said receiving timing signal deriver and said local transmission timing signal generator, and
- a synthetic preamble generator responsive to said control circuit.
Dependencies are inferred from the claim text.