Digital signal processing circuit

Abstract

A digital signal processing circuit has a memory circuit to store reproduction data and recording information, a reproduction signal processing circuit for demodulating a reproduction signal to thereby obtain the reproduction data and the recording information and for storing the reproduction data and the recording information into the memory circuit, an error detecting and correcting circuit for executing an error detecting and correcting process on the reproduction data, and a data output circuit for outputting the reproduction data stored in the memory circuit on the basis of the recording information. The digital signal processing circuit incorporates a plurality of multiplex coincidence detecting circuits for sequentially detecting whether the recording information coincides or not and for outputting the recording information, in which the coincidence result is respectively obtained by only a predetermined number of times, to the memory circuit; and a selecting circuit for selectively outputting the recording information to the plurality of multiplex coincidence detecting circuits in accordance with the kind of recording information.

Dependencies are inferred from the claim text.