Data processing system having scan testing using set latches for selectively observing test data

In a data processing system, a method of scan testing predetermined logic circuitry of the system for obtaining test data related to transistor structural fault testing of the system, comprising the steps of:

• receiving and storing predetermined input scan test data and selectively providing a plurality of predetermined test data signals;
• coupling the test data signals to the predetermined logic circuitry during a test mode of operation of the system;
• providing output driver circuits within the predetermined logic circuitry to provide output control signals in response to receipt of the test data signals;
• providing a data path which provides and receives data from a data bus, the data path having a plurality of registers, each of the registers having a control input connected via a conductor to a predetermined one of the output control signals;
• connecting a plurality of latch circuits in series, each latch circuit having a control terminal coupled to the data path and receiving a predetermined one of the output control signals which has been routed to the data path before being routed to the plurality of latch circuits;
• initializing each of the latch circuits to a first predetermined logic state;
• controlling each of the latch circuits with a predetermined one of the output control signals, each of the latch circuits either being set to a second predetermined logic state or remaining in the first predetermined logic state;
• and
• scanning the plurality of latch circuits to output a resultant logic state of each of the latch circuits and provide a test signal indicating transistor structural fault information of transistors in the logic circuitry including transistors of the clocked output driver circuits and indicating electrical continuity from the driver circuits to the latch circuits.

A data processing system having scan testing for providing test data related to transistor structural testing of the system, comprising:

• a first plurality of test scan latch circuits for serially receiving and storing predetermined input scan data and having a plurality of parallel coupled outputs, each output providing a predetermined test data value;
• logic circuit means for performing predetermined data processing functions in the data processing system, the logic circuit means having a plurality of parallel inputs coupled to the test scan latch circuits and having a plurality of clocked output driver circuits for selectively providing output control signals during each of a functional mode of operation and a test mode of operation, the test mode of operation being entered in response to receipt of the predetermined test data value from each of the test scan latch circuits;
• a plurality of data registers coupled to the logic circuit means for communicating data within the system via a data input/output bus during the functional mode of operation, the output control signals selecting predetermined data registers to communicate data;
• and
• a second plurality of latch circuits, each latch circuit of the second plurality having a control input connected to the plurality of data registers and receiving a predetermined one of the output control signals, each of the output control signals being routed to at least one of the data registers prior to being connected to a predetermined one of the latch circuits of the second plurality, each latch circuit of the second plurality being placed in a first logic state prior to entering the test mode of operation, each of the output control signals either setting a predetermined one of the latch circuits of the second plurality to a second predetermined logic state or allowing the predetermined one of the latch circuits of the second plurality to remain in the first logic state, each of the latch circuits of the second plurality providing a test signal in response to clocking the second plurality of latch circuits, the test signal indicating both transistor fault information of transistors in the logic circuit means including the clocked output driver circuits and indicating electrical continuity from the clocked output driver circuits to each control input of the second plurality of latch circuits.