Means and method for detecting and correcting microinstruction errors

In a data processing system, a combination comprising:

• a addressable microinstruction memory means for storing microinstructions, said memory means including a spare memory portion which is addressed concurrently therewith;
• execution means for executing a microinstruction applied thereto;
• means for accessing a microinstruction from said microinstruction memory means for providing a microinstruction output along with a spare memory portion output;
• means for applying an accessed microinstruction to said execution means, said means for applying including configurable multiplexer means for determining whether the output of said spare memory is to be substituted for a corresponding microinstruction portion;
• microinstruction error detection means to which an accessed microinstruction is applied concurrently with the application of the accessed microinstruction to said execution means, said microinstruction error detection means being operative to abort execution of the accessed microinstruction when an error is detected therein;
• and
• microinstruction error correction means responsive to the detection of a microinstruction error by said error detection means for causing a correct microinstruction to be applied to said execution means;
• said microinstruction error correction means also providing for detecting a hard error in a microinstruction and in response thereto loading said spare portion with corrective data and also configuring said multiplexer means so that when the microinstruction having the hard error is accessed corrective data from said spare portion is substituted for the microinstruction portion for which a hard error was detected.

In a data processing system, a combination comprising:

• a microinstruction memory arranged in bit-storing columns and having a spare bit column;
• execution means for executing a microinstruction applied thereto;
• addressing means for applying a microinstruction address to said microinstruction memory for accessing output bits therefrom, said output bits including microinstruction bits along with a bit from said spare bit column;
• configurable multiplexer means to which said output bits are applied;
• a microinstruction register coupled to said configurable multiplexer means for receiving and storing output bits therefrom constituting a microinstruction;
• selection means for selectively configuring said multiplexer means to substitute the bit from said spare bit column in place of a microinstruction bit,
• means for applying a microinstruction in said microinstruction register to said execution means;
• microinstruction error detection means to which a microinstruction is applied from said microinstruction register concurrently with the application of the microinstruction to said execution means, said microinstruction error detection means being operative to abort execution of the accessed microinstruction and also prevent accessing of a next microinstruction when an error is detected in an accessed microinstruction;
• and
• microinstruction error correction means responsive to the detection of a microinstruction error by said error detection means for causing a correct microinstruction to be applied to said execution means;
• said microinstruction error correction means providing for detecting a hard error in a microinstruction bit and in response thereto loading said spare bit column to correct the error, said microinstruction error correction means also signaling said selection means to reconfigure said multiplexer means so that when the microinstruction having the hard error is accessed the bit from said spare bit column is substituted for the microinstruction bit for which a hard error was detected.

In a data processing system having microinstruction execution means for performing data processing operations in response to microinstructions applied thereto, a method comprising the steps of:

• providing a microinstruction memory arranged in bit-storing columns along with an additional microinstruction memory portion providing at least one spare column of bits;
• providing an address register for storing a microinstruction address;
• applying a microinstruction address in said address register to said microinstruction memory for producing microinstruction output bits including at least one output bit from said additional microinstruction memory portion;
• selectively applying particular ones of said microinstruction output bits constituting a microinstruction to a microinstruction register;
• applying a microinstruction in said microinstruction register to said execution means;
• controlling said selectively applying such that in the absence of a hard error the microinstruction applied to said execution means does not include an output bit from a spare column of said additional microinstruction memory portion;
• concurrently with said selectively applying, checking the microinstruction applied to said execution means to detect whether the microinstruction contains an error;
• in response to detecting an error, aborting the execution of the microinstruction which produced the error;
• detecting a hard error by determining whether a detected error was previously detected a predetermined number of times;
• and
• in response to detecting a hard error, storing correct data in a corresponding column of said additional microinstruction memory portion while also modifying the step of controlling such that each time a microinstruction is subsequently addressed by said address register the microinstruction output bits applied to said microinstruction register contains the output bit from said corresponding column substituted for the one in the column which produced the hard error.