Circuit arrangement for clock regeneration in clock-controlled information processing systems

In a clock-controlled telephone system, particularly a centrally-controlled telephone switching system.

• a switching matrix network providing an incoming clock;
• redundant data paths coupled to said switching matrix network and including respective ends, and clock-controlled compensation memories connected at said second ends of said redundant data paths for local compensation of transient times, so that an alternate route for data transmission is available in case of fault;
• a clock-controlled switch-over device for switching between said redundant data path;
• and
• a clock generator connected to provide said memories and said switch-over device with a clock grid of uniform phase and frequency from the incoming clock which is distorted due to transient time and component tolerances, said clock generator comprising
• a flip-flop including a set input connected to receive said incoming clock which is to be regenerated, a reset input, and output means including a first output for providing a first output signal and a second output for providing a second output signal which is inverted with respect to said first output signal, and
• delay means connected between said output means and said reset input of said flip-flop and having a delay time which is shorter than the period of the incoming clock.