Configuration of SRAMS as logical FIFOS for transmit and receive of packet data

For a network adapter controlling flow of data arranged in packets between a system memory and a network, comprising:

• first memory means for storing transmit data;
• means for configuring said first memory means as a first logical first in-first out memory (transmit FIFO);
• means for detecting a request for transmission of data to the network;
• first means responsive to said request for transmission to said network for transferring data from said system memory, one packet at a time, to said transmit FIFO;
• second means for transferring said data from said transmit FIFO to said network while said transmit FIFO is receiving data from said system memory;
• second memory means for storing receive data;
• means for configuring said second memory means as a second logical first in-first out memory (receive FIFO);
• means for detecting data incoming from the network to be stored in the system memory;
• third means for transferring data from said network to said receive FIFO;
• and
• fourth means detecting a predetermined amount of data in said receive FIFO for transferring said predetermined amount of data from said receive FIFO to said system memory while said receive FIFO is receiving data from said network.

For a network adapter controlling flow of data arranged in packets between a system memory and a network, apparatus comprising:

• first buffer memory means for storing data to be transmitted on said network;
• means for configuring said first buffer memory means as a first logical first in-first out memory (transmit FIFO);
• first detecting means for detecting a request for transmission of data to the network;
• means responsive to said first detecting means for transferring data from said system memory, one packet at a time, to said transmit FIFO;
• second detecting means for detecting the presence in said transmit FIFO of at least one full packet of said transmit data;
• third detecting means for detecting the presence in said transmit FIFO of at least a predetermined amount of transmit data;
• means responsive to said second and third detecting means for transferring data from said transmit FIFO to said network when either at least a full packet of data or at least said predetermined amount of data is stored in said transmit FIFO;
• second memory means for storing data received from said network;
• means for configuring said second memory means as a second logical first in-first out memory (receive FIFO);
• fourth detecting means for detecting data incoming from the network to be stored in the system memory;
• means for transferring data from said network to said receive FIFO;
• fifth detecting means for detecting a predetermined amount of data stored in said receive FIFO from said network;
• and
• means responsive to said fifth detecting means for transferring said predetermined amount of data from said receive FIFO to said system memory.

For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet bit, a network controller, comprising:

• a random access memory;
• means for defining in said random access memory a buffer memory configured as a transmit FIFO;
• means for transferring from said system memory means to said transmit FIFO successive frames of data demarked by said end of packet (tag) bits and forming a queue to be transmitted;
• first detector means for detecting said tag bits to determine that at least one full frame of data is stored in said transmit FIFO;
• second detector means for detecting that at least a predetermined amount of data is stored in said transmit FIFO;
• and
• means responsive to at least one of said first and second detector means for transmitting the content of said transmit FIFO to a network.

For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet bit, a network controller, comprising:

• a random access memory;
• means for defining in said random access memory a buffer memory configured as a receive FIFO;
• means for storing in said receive FIFO incoming receive data packets demarked by said end of packet (tag) bits and forming a receive queue;
• means for storing a receive data threshold value;
• means for detecting that the content of said receive FIFO exceeds said receive data threshold value;
• and
• means responsive to said detecting means for transferring data from said receive FIFO to said system memory means.

A method of controlling flow of data arranged in packets each having one end marked by a tag bit between a system memory and a network bus, comprising the steps of:

• configuring a first memory as a first logical first in-first out memory (transmit FIFO);
• detecting a request for transmission of data to the network bus;
• in response to a request for transmission to said network bus, transferring data from said system memory, one packet at a time, to said transmit FIFO;
• detecting the tag bit defining the end of a packet;
• and
• in response to occurrence of the tag bit transferring said data from said transmit FIFO to said network bus while data is incoming from said system memory to said transmit FIFO.

For an adapter for a network including a plurality of processors and system memory means for storing frames of data arranged in a plurality of different queues, the frames of each queue having a priority different from the priorities of frames of data of the other queues, apparatus for controlling transmission of said frames of data between said system memory means and said network, comprising:

• a buffer memory configured to have a plurality of separate logical first in-first out (FIFO) memory regions for storing respectively the plurality of queues of framed data to be transmitted to or received from the network, each of said FIFO memory regions storing one of said queues;
• first data controller means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding FIFO memory regions of said buffer memory;
• and
• means for transmitting said framed data, stored in said FIFO memory regions of said output buffer memory, to said network while data is incoming from said system memory means to said FIFO memory regions of said buffer memory.

For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors, each including a system memory means for storing frames of data arranged in a plurality of queues, each queue having a transmit priority different from the transmit priorities of the other queues, and an optical medium forming a digital data communication path among said processors, a network controller, comprising:

• first means implementing a timed token data protocol for accessing said optical medium;
• a random access memory forming an output buffer;
• second means for configuring in said random access memory a plurality of separate logical FIFOs for respectively storing therein said plurality of queues having different transmit priorities, each of said logical FIFOs storing one of said queues;
• means for controlling flow of said framed data to corresponding logical FIFOs in said buffer memory, said framed data flow controlling means including first means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding logical FIFOs in said buffer memory, and second means for transmitting said framed data, stored in said logical FIFOs to said medium while data is incoming from said system memory means to said FIFOs in said buffer memory.

For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors each having system memory means for storing frames of data arranged in a plurality of different queues, the frames of each queue having a priority different from the priorities of frames of data of the other queues, an optical medium forming a digital data communication path among said processors, an output buffer memory configured to have a plurality of separate logical first in-first out (FIFO) memory regions for storing respectively the plurality of queues of framed data to be transmitted to the optical medium, and means for transmitting said framed data, stored in said logical FIFO memory regions of said output buffer memory, to said optical medium, each of the FIFO memory regions storing one of the queues:

• a method of interfacing said system memory means and said optical medium, comprising the steps of:
• accessing said optical medium upon a token capture in response to predetermined conditions, and in response,
• controlling movement of framed data to be transmitted to said optical medium by
• (a) transmitting said framed data from said system memory means to corresponding logical FIFOs in said output buffer memory, one queue at a time in order of priority, and
• (b) transmitting said framed data stored in said logical FIFOs to said optical medium while data is incoming from said system memory means to said logical FIFOs.

For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet (tag) bit, a network controller, comprising:

• a random access memory;
• means for defining in said random access memory a buffer memory configured as a transmit FIFO;
• means for transferring from said system memory means to said transmit FIFO successive frames of data demarked by said end of packet (tag) bits and forming a queue to be transmitted;
• first detector means for detecting that at least one full frame of data is stored in said transmit FIFO;
• second detector means for detecting that at least a predetermined amount of data is stored in said transmit FIFO;
• and
• means responsive to at least one of said first and second detector means for transmitting the content of said transmit FIFO to a network;
• wherein said transmit FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said transmit FIFO, and a SHADOW WRITE pointer pointing to the end of a full frame stored in said transmit FIFO, wherein said first detector means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet (tag) bit, a network controller, comprising:

• a random access memory;
• means for defining in said random access memory a buffer memory configured as a receive FIFO;
• means for storing in said receive FIFO incoming receive data packets demarked by said end of packet (tag) bits and forming a receive queue;
• means for storing a receive data threshold value;
• means for detecting that the content of said receive FIFO exceeds said receive data threshold value;
• and
• means responsive to said detecting means for transferring data from said receive FIFO to said system memory means;
• wherein said receive FIFO is defined by START and END pointers, and including READ and WRITE pointers, a SHADOW WRITE pointer pointing to the beginning of the latest frame being received in the receive FIFO, and a receive threshold value, wherein said receive data is transferred to said system memory means when said write pointer exceed said threshold value and when said receive data is to be flushed, the write pointer is replaced by the shadow write pointer.

For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors, each including a system memory means for storing frames of data arranged in queues and having a plurality of different transmit priorities, and an optical medium forming a digital data communication path among said processors, a network controller, comprising:

• first means implementing a timed token data protocol for accessing said optical medium;
• a random access memory forming a buffer memory;
• and
• second means for configuring in said random access memory a plurality of logical FIFOs for storing therein said queued frames of data having respectively said plurality of different transmit priorities;
• means for controlling flow of said framed data to corresponding logical FIFOs in said buffer memory, said framed data flow controlling means including first means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding logical FIFOs in said buffer memory, and second means for transmitting said framed data, stored in said logical FIFOs to said medium while data is incoming from said system memory means to said FIFOs in said buffer memory;
• wherein each said logical FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said logical FIFO and a SHADOW WRITE pointer pointing to the end of a full frame stored in said logical FIFO, and wherein said data flow controlling means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.