Communications controller for use with a computer and a plurality of ISDN terminals

A communications controller (CCS) for connection between a bus (PSB) associated with at least one host system (HOST) and a plurality of terminals of at least one network (RE.sub.1 -RE.sub.2) which are connected together through at least one time-multiplexed digital link (S.sub.0) that includes a plurality of data channels (C.sub.1 to C.sub.6) for transferring frames, the data channels being managed according to specific protocols and being supported by at least one transmission line (LE.sub.1 -LR.sub.1, LE.sub.2 -LR.sub.2), said communications controller comprising:

• a base unit (BA), connected to said bus (PSB), for managing and effecting the transfer of frames (TR.sub.1 to TR.sub.2 . . . ) over each one of said plurality of data channels (C.sub.1 to C.sub.6);
• and
• a peripheral unit (PER) connected both to said base unit (BA) and to said transmission line, for ensuring time-multiplexing and demultiplexing of various data channels of the link, and for transmitting data to the network and receiving data from the network,
• wherein said base unit (BA) includes:
• a first memory (MV.sub.1) for storing frames before they are transferred, and for managing transfer of the frames to various channels assigned thereto;
• a first control processor (MP.sub.1), for transferring frames from the host to the network (RE.sub.1 -RE.sub.2) and vice versa, connected to the bus and associated with said first memory (MV.sub.1),
• said first control processor (MP.sub.1) executing a communications program (CNS) which is written in said first memory (MV.sub.1) when the communications controller (CCS) is initialized;
• a second processor (MP.sub.2), communicating with the first control processor (MP.sub.1), for transferring each of frames (TR.sub.1, TR.sub.11), channel by channel, from said first memory (MV.sub.1) to the peripheral unit and then to the network, and vice versa;
• and
• a second memory (MV.sub.2) associated with said second processor (MP.sub.2),
• said second processor (MP.sub.2) executing a microprogram architecture (AML) which is written into said second memory (MV.sub.2) at the time the controller is initialized,
• said microprogram architecture (AML) having a nucleus (NY), a communications interface (IC) for dialogues between the communications program (CNS) and the microprogram architecture (AML), and at least as many microprogram modules (TC.sub.0, TC.sub.1, . . ., TC.sub.7) as there are channels.
• each channel being associated with a microprogram module which transfers frame assigned to this channel from the first memory (MV.sub.1), to the network via the peripheral part, and vice versa,
• each microprogram module being independent of other microprogram modules, its sequencing being organized in real-time by the nucleus (NY),
• and wherein said peripheral part (PER) includes:
• a coupler (CO, CO.sub.1 -CO.sub.2) for all the channels, controlled by said second processor (MP.sub.2) and connected to the transmission line, coming from or going to said first memory (MV.sub.1), and for providing multiplexing or demultiplexing of the data upon sending or upon receiving.