Memory with page mode
AssigneeInternational Business Machines Corporation
InventorsMatthew D. Bates, Adrian C. Gay, Roderick M. West, Todd Williams
Life of this patent
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Abstract
In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.
Claims12
In a memory comprising first and second arrays, each array comprising a plurality f memory cells arranged into rows and columns, each of said rows having a respective binary address, a method of accessing a plurality of rows having sequential binary address in response to receipt by the memory of a single binary address signal, comprising the steps of:
- a) accessing a first row of memory cells in said first array;
- b) accessing a first row of memory cells in said second array, while restoring said first row of memory cells in said first array;
- c) accessing a second row of memory cells in said first array, while restoring said second row of memory cells in said first array;
- (d) accessing a second row of memory cells in said second array, while restoring said second row of memory cells in said first array;
- and
- e) restoring said second row of memory cells in said second array.
A memory comprising first and second arrays, each array comprising a plurality of memory cells arranged into rows that are accessed in response to a binary address signal, each of said rows being assigned binary addresses, wherein first and second rows having adjacent binary addresses are located n said first and second arrays, respectively, and means for accessing said first and second arrays sequentially by accessing rows having adjacent binary addresses by sequentially incrementing or decrementing a received binary address signal.
A memory having a plurality of rows and columns and operable in a given page mode cycle such that a row address is selected for a row cycle and within said row cycle a plurality of column cycles are performed to access the memory at selected column addresses, wherein said memory additionally comprises control means for stepping the row address for selected column cycles within said given page mode cycle.
In a memory addressable by row and by column and operable in page mode such that a row address is selected for a row cycle and within said row cycle a plurality of column cycles are performed to access the memory at selected column addresses, a method of changing the row accessed for selected column accesses comprising the steps of:
- a) setting the memory in a selected row change mode in response to a mode signal which is supplied to the memory when a row address strobe becomes active, said row change mode defining a row address step to be performed in response to a row change signal;
- and
- b) stepping the row address as defined by the row change mode in response to a row change signal supplied to the memory when a column address strobe becomes active.
Dependencies are inferred from the claim text.