Waveform shaping circuit and digital signal analyzing apparatus using the same

A waveform shaping circuit comprising:

• a level shifter for variably controlling a direct current (DC) off-set voltage of an input digital signal;
• a comparator for comparing a digital signal output from said level shifter with a predetermined reference voltage so as to shape a waveform of the input digital signal and outputting a shaped digital signal;
• a maximum value detector for detecting a maximum value of a digital signal output from said level shifter;
• a minimum value detector for detecting a minimum value of the digital signal output from said level shifter;
• center voltage detecting means for detecting a center voltage between the maximum value detected by said maximum value detector and the minimum value detected by said minimum value detector;
• a subtractor for detecting a difference voltage between the center voltage output from said center voltage detecting means and the predetermined reference voltage and outputting an error signal obtained by amplifying a detected difference voltage so as to equalize the center voltage to the predetermined reference voltage by changing the DC offset voltage;
• and
• a low-pass filter for selecting a signal component having a frequency lower than a predetermined frequency from the error signal output from said subtractor and outputting a control signal so as to control the DC off-set voltage to said level shifter.

A signal analyzing apparatus comprising:

• a level shifter for variably controlling a direct (DC) off-set voltage of an input digital signal;
• a comparator for comparing a digital signal output from said level shifter with a predetermined reference voltage so as to shape a waveform of the input digital signal and outputting a shaped digital signal;
• intermediate voltage detecting means for detecting and outputting an intermediate voltage between high- and low-level voltages of a digital signal output from said level shifter;
• first control means for receiving the intermediate voltage output from said intermediate voltage detecting means and the predetermined reference voltage and outputting a control signal for changing the DC offset voltage to equalize the intermediate voltage to the predetermined reference voltage to said level shifter;
• a variable delay circuit for delaying a phase of an input clock signal;
• a discriminator for receiving an output from said comparator and an output from said variable delay circuit and determining a code of the output signal from said comparator at a timing determined by a delayed clock signal delayed by said variable delay circuit;
• an error measuring unit for comparing a determination signal from said discriminator with a reference signal corresponding to the input digital signal and outputting an error signal;
• and
• second control means for receiving an output from said error measuring unit, detecting an intermediate delay amount of delay amounts corresponding to error signals having maximum values adjacent to each other, and sending the intermediate delay amount to said variable delay circuit, to thereby reduce the error signal output from said error measuring unit.

A signal analyzing apparatus comprising:

• a 1eveI shifter for variably controlling a direct current (DC) offset voltage of an input digital signal;
• a comparator for comparing a digital signal output from said level shifter with a predetermined reference voltage so as to shape a waveform of the input digital signal and outputting a shaped digital signal;
• intermediate voltage detecting means for detecting and outputting an intermediate voltage between high-and low-level voltages of a digital signal output from said level shifter;
• control means for receiving the intermediate voltage output from said intermediate voltage detecting means and the predetermined reference voltage and outputting a control signal for changing the DC offset voltage to equalize the intermediate voltage to the predetermined reference voltage to said level shifter;
• a discriminator for receiving an input clock signal and an output from said comparator as a signal to be discriminated to determine a code of the signal to be discriminated at a timing determined by the input clock signal;
• and
• an error measuring unit for comparing a determination signal from said discriminator with a reference signal corresponding to the input digital signal, to thereby output an error signal.

A signal analyzing apparatus comprising:

• a level shifter for variably controlling a direct current (DC) offset voltage of an input digital signal;
• a comparator for comparing a digital signal output from said level shifter with a predetermined reference voltage so as to shape a waveform of the input digital signal and outputting a shaped digital signal;
• intermediate voltage detecting means for detecting and outputting an intermediate voltage between high-and low-level voltages of a digital signal output from said level shifter;
• control means for receiving the intermediate voltage output from said intermediate voltage detecting means and the predetermined reference voltage to output a control signal for changing the DC offset voltage to equalize the intermediate voltage to the predetermined reference voltage to said level shifter;
• holding means for holding the control signal output from said control means;
• stopping means for stopping an operation of said intermediate voltage detecting means when the control signal is held by said holding means;
• a discriminator for receiving an input clock signal and an output from said comparator as a signal to be discriminated to determine a code of the signal to be discriminated at a timing determined by the input clock signal;
• and
• an error measuring unit for comparing a determination signal from said discriminator with a reference signal corresponding to the input digital signal to output an error signal.