Automatic delay adjustment for static timing analysis

A static timing analysis system, including a programmed computer apparatus for analyzing timing delays in a logic design, comprising:

• means in the programmed computer apparatus for simulating a logic design by providing representations of a logic clock, logic elements, and connections between the logic elements, the logic elements including clocked elements triggered by the logic clock;
• a signal representation in the programmed computer apparatus of a signal propagating in the logic design, the signal representation including a clock tag identifying a first phase of the logic clock during which the signal is clocked in the logic design;
• propagating means in the programmed computer apparatus for applying the signal representation to a representation of a clocked element in the logic design, the clocked element being triggered by a second phase of the logic clock to move the signal to an output of the clocked element;
• and
• delay means in the programmed computer apparatus connected to the propagating means and responsive to the clock tag for comparing the first phase and second phase to produce a representation of the cumulative delay of the signal representation through the clocked elements.

A computer-implemented method for conducting static timing analysis of a logic design, the logic design including a multi-phase logic clock, circuit logic elements, and connections between the circuit logic elements, the circuit logic elements including clocked elements which are triggered by the multi-phase clock, the method including the steps of:

• representing a first signal in the logic design with a first data object including a first field containing a clock value representing a clock phase during which the first signal is clocked in the logic design and a second field containing a time value representing a time by which the first signal is delayed in the logic design;
• simulating the application of the first signal to an input pin of a clocked element which is triggered by a particular phase of the multi-phase clock;
• determining a cumulative delay value representing the cumulative delay of the first signal at an output pin of the clocked element in response to the clock phase in the first field and the particular phase;
• and
• changing the first field to a value representing the particular phase and changing the second field value to the cumulative delay value.

In a computer apparatus programmed for analyzing timing delays in a multi-phase-clock logic network under static conditions, an improvement for analyzing signal delay through the logic network, the improvement comprising:

• simulating means for providing a logical counterpart of the logic network which represents a multi-phase clock, elements of the logic network and connections between those elements, the elements including clocked elements which respond to the multi-phase clock by storing data signals;
• a first data object representing a data signal propagating from an element in the logic network, the first data object including a first data field representing a first phase of the multi-phase clock during which said data signal is clocked by the logic network and a second data field representing a first time by which the data signal is delayed in the logic network;
• a second data object representing said data signal, the second data object including a first data field representing a second phase of the multi-phase check during which said data signal is clocked by the logic network and a second data field representing a second time by which the data signal is delayed in the logic network;
• propagating means for applying the first and second data objects to a representation of a clocked element being triggered by a third phase of the multi-phase clock;
• and
• delay means connected to the propagating means for comparing the first and second phases represented by the first fields in the first and second data objects, respectively, with a representation of the third phase to change the second field of the first or second data object to a path delay value representing the cumulative delay value of the data signal through the clocked element.