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US 5,210,639 AGranted
Dual-port memory with inhibited random access during transfer cycles with serial access
AssigneeTexas Instruments Incorporated
InventorsDonald J. Redwine, Raymond Pinkham
Life of this patent
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Abstract
In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.
Claims15
An integral memory device having random and serial access capability, comprising the following elements:
- an internal array of rows and columns of addressable memory cells;
- a plurality of address input terminals for receiving an address from external of said memory device;
- address circuitry for selecting a memory cell in said array responsive to said address input terminals receiving an address;
- random access input circuitry for writing externally received data to said memory cell selected by said address circuitry;
- random access output circuitry for accessing the contents of said memory cell selected by said address circuitry and presenting it externally of said memory device;
- a register comprised of a plurality of memory cells internal of said device;
- memory transfer circuitry for transferring the contents of selected memory cells of said array into the memory cells of said register;
- serial output circuitry coupled to at least one memory cell in said register for presenting the contents of said memory cell in said register to external of said device;
- transfer control circuitry, responsive to a transfer control signal and internal of said device, for selectively enabling and disabling said memory transfer circuitry so that, while said memory transfer circuitry is disabled, data may be randomly written to and read from any of said memory cells in said array independently from the presentation of data by said serial output circuitry;
- serial transfer circuitry responsive to a serial clock signal for transferring to said serial output circuitry the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented externally of said device by said serial output circuitry;
- and
- a buffer circuit, internal of said device, coupled to said random access output circuitry and responsive to said transfer control circuitry, for selectively inhibiting said random access output circuitry from externally presenting the contents of said memory cell selected by said address circuitry during such time as said memory transfer circuitry is enabled;
- wherein all of said elements are included in said integral memory device,
10 more elements
A dual-port integral memory device having random and serial access capability, comprising the following elements;
- an internal array of memory cells;
- a serial register, internal of said device, coupled to said array of data transfer circuitry and including a serial output coupled to a serial access output terminal;
- address circuitry, receiving an address from address input terminals, for randomly selecting a single memory cell from said array for random access operation or a plurality of memory cells for serial access operation;
- random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry;
- random access output circuitry for presenting the contents of said memory cell selected by said address circuitry to external of said device;
- a transfer control circuit, coupled to a control terminal providing control signals, to select between serial access operation and random access operation, said control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation;
- and
- first output control circuitry internal of said device, coupled to said random access output circuitry and responsive to said control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated;
- wherein all of said elements are included in said integral memory device.
6 more elements
A data processing system comprising:
- a data processing unit;
- a utilization device utilizing data processed by said data processing unit;
- and
- an integral memory device for storing data and having serial and random access capability, the memory device comprising the following elements:
- an internal array of memory cells;
- a serial register, internal of said device, coupled to said array by data transfer circuitry and including a serial output coupled to a serial output terminal;
- address circuitry, receiving an external address from address input terminals, for randomly selecting a single memory cell from said array for random access operation of selecting a plurality of memory cells for serial access operation;
- random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry;
- random access output circuitry;
- a transfer control circuit, coupled to a control terminal, for providing at least one control signal to select between serial access operation and random access operation, said transfer control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation;
- and
- first output control circuitry, internal of said device coupled to said random access output circuitry and responsive to said transfer control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated;
- wherein all of said elements are comprised in said integral memory device.
10 more elements
Dependencies are inferred from the claim text.