Glitch detection circuit and method

A glitch detection circuit comprising:

• A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data;
• state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means, having 2.sup.n output lines, for decoding a logic state of n-bit digital data fed from said A/D converting means, to select one of said 2.sup.n output lines corresponding to one of 2.sup.n logic states of the n-bit digital data to represent the logic state of the n-bit digital data, and a plurality of binary value storing means, each of said binary value storing means being connected to one of the 2.sup.n output lines of said decode means, for storing the logic state represented by said decode means;
• discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means;
• and
• storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.

A glitch detection method comprising the steps of:

• (a) converting an input signal into successive n-bit digital data by sampling the input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval;
• (b) holding a distribution state of a first set of n-bit digital data produced by said conversion of said input signal at a first sampling interval during the acquisition interval by decoding the first set of n-bit digital data into 2.sup.n -bit data and holding the 2.sup.n -bit data;
• (c) changing the distribution state by decoding a next set of n-bit digital data produced by said conversion of said input signal at a next sampling interval during the acquisition interval into 2.sup.n -bit data, comparing the 2.sup.n -bit data of said next set with the 2.sup.n -bit data of said first set, and updating one or more bits of the held 2.sup.n -bit data on the basis of the comparison;
• (d) repeating step (c) with a succeeding set of n-bit digital data produced by said conversion of said input signal at a succeeding sampling interval during the acquisition interval;
• (e) detecting, after completing steps (a)-(d), a maximum value and a minimum value of the n-bit digital data produced by said conversion during the acquisition interval;
• and
• (f) storing the maximum value and the minimum value of the n-bit digital data produced by said conversion during the acquisition interval.

A glitch detection circuit comprising:

• A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data;
• state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means for decoding n-bit digital data produced by said A/D converting means during said acquisition interval to select one of 2.sup.n logic states of said digital data, a plurality of binary value storing means, each of said binary value storing means corresponding to a respective one of said 2.sup.n logic states, and means for setting respective ones of said binary value storing means which correspond to logic states selected by said decode means;
• discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means;
• and
• storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.